专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07385539B2 All-digital phase locked loop (ADPLL) system 有权
标题翻译：全数字锁相环（ADPLL）系统
公开(公告)号：US07385539B2
公开(公告)日：2008-06-10
申请号：US11675003
申请日：2007-02-14
申请人： Frank Vanselow , Chung San Roger Chan
发明人： Frank Vanselow , Chung San Roger Chan
IPC分类号： H03M3/00
CPC分类号： H03L7/08 , H03L2207/50
摘要： An all-digital phase locked loop system for generating an oscillator output signal under control of a digital reference input. The system comprises a digitally controlled oscillator, a digital loop filter for generating a multiple bit digital control signal for the digitally controlled oscillator, a sigma-delta modulator for generating an additional 1-bit digital control signal for the digitally controlled oscillator, a digital divider dividing the oscillator output signal and providing a digital divided signal, and a digital adder with a first, additive input to which the digital reference input is applied and a second, subtractive input to which the digital divided signal is applied. The digital adder provides a digital output, the most significant bits of which are applied to an input of the digital loop filter and the least significant bits of which are applied to an input of the sigma-delta modulator. In the preferred embodiment, the sigma-delta modulator is of a two-stage MASH configuration.
摘要翻译：全数字锁相环系统，用于在数字参考输入的控制下产生振荡器输出信号。该系统包括数字控制振荡器，用于产生用于数字控制振荡器的多位数字控制信号的数字环路滤波器，用于产生用于数字控制振荡器的附加1位数字控制信号的Σ-Δ调制器，数字分频器分频振荡器输出信号并提供数字分频信号，以及数字加法器，其具有施加数字参考输入的第一加法输入和施加数字分频信号的第二减法输入。数字加法器提供数字输出，其最高有效位被施加到数字环路滤波器的输入，并且其最低有效位被施加到Σ-Δ调制器的输入端。在优选实施例中，Σ-Δ调制器是两级MASH配置。

2. 发明申请

US20080159459A1 Methods and apparatus to provide clock resynchronization in communication networks 有权
标题翻译：在通信网络中提供时钟重新同步的方法和装置
公开(公告)号：US20080159459A1
公开(公告)日：2008-07-03
申请号：US11653534
申请日：2007-01-16
申请人： Chung San Roger Chan , Richard M. Prentice , Woo Jin Kim
发明人： Chung San Roger Chan , Richard M. Prentice , Woo Jin Kim
IPC分类号： H04L7/00
CPC分类号： H04L7/033
摘要： Methods and apparatus to provide clock resynchronization in communication networks are disclosed. An example method of clock resynchronization disclosed herein comprises determining a vote based on adjacent samples occurring within a single bit interval in a sampled data stream, wherein the vote comprises an early vote when the adjacent samples indicate a sampling phase of a sampling clock is early relative to a center position in the bit interval and wherein the vote comprises a late vote when adjacent samples indicate the sampling phase is late relative to the center position, tracking a running difference between a number of early votes and a number of late votes in a plurality of votes corresponding to a plurality of adjacent samples, and adjusting the sampling phase when the running difference reaches a threshold.
摘要翻译：公开了在通信网络中提供时钟再同步的方法和装置。本文公开的时钟重新同步的示例性方法包括基于在采样数据流中的单个位间隔内发生的相邻采样来确定投票，其中当相邻采样指示采样时钟的采样相位为早期相对时，投票包括早期投票到所述比特间隔中的中心位置，并且其中所述投票包括晚期投票，当相邻样本指示所述采样阶段相对于所述中心位置较晚时，跟踪多个早期投票与多个晚期投票数之间的差异的投票对应于多个相邻样本，并且当运行差达到阈值时调整采样相位。

3. 发明授权

US06624670B2 High speed voltage mode differential digital output driver with edge-emphasis and pre-equalization 有权
标题翻译：高速电压模式差分数字输出驱动器，具有边缘强调和预均衡
公开(公告)号：US06624670B2
公开(公告)日：2003-09-23
申请号：US10098046
申请日：2002-03-14
申请人： Robert F. Payne , Chung San Roger Chan , Samuel M. Palermo
发明人： Robert F. Payne , Chung San Roger Chan , Samuel M. Palermo
IPC分类号： H03B100
CPC分类号： H04L25/028 , H03K19/01721 , H03K19/018521 , H04L25/0272 , H04L25/03878
摘要： A differential driver includes two feedback loops 20 and 22, and two inverter pairs 24 and 26. The two feedback loops 20 and 22 regulate the source voltages for the two inverter pairs 24 and 26 to the reference voltages VREFHI and VREFLO. The two inverter pairs 24 and 26 switch the output load RL and CL between the two regulated voltages in response to the input voltages IN+ and IN−. The reference voltages VREFHI and VREFLO are created by a reference cell and set the output high and low voltages.
摘要翻译：差分驱动器包括两个反馈回路20和22以及两个反相器对24和26.两个反馈回路20和22将两个反相器对24和26的源电压调节到参考电压VREFHI和VREFLO。两个逆变器对24和26响应于输入电压IN +和IN-来切换两个调节电压之间的输出负载RL和CL。参考电压VREFHI和VREFLO由参考单元创建，并设置输出高低电压。

4. 发明授权

US08000425B2 Methods and apparatus to provide clock resynchronization in communication networks 有权
标题翻译：在通信网络中提供时钟重新同步的方法和装置
公开(公告)号：US08000425B2
公开(公告)日：2011-08-16
申请号：US11653534
申请日：2007-01-16
申请人： Chung San Roger Chan , Richard M Prentice , Woo Jin Kim
发明人： Chung San Roger Chan , Richard M Prentice , Woo Jin Kim
IPC分类号： H04L7/00
CPC分类号： H04L7/033
摘要： Methods and apparatus to provide clock resynchronization in communication networks are disclosed. An example method of clock resynchronization disclosed herein comprises determining a vote based on adjacent samples occurring within a single bit interval in a sampled data stream, wherein the vote comprises an early vote when the adjacent samples indicate a sampling phase of a sampling clock is early relative to a center position in the bit interval and wherein the vote comprises a late vote when adjacent samples indicate the sampling phase is late relative to the center position, tracking a running difference between a number of early votes and a number of late votes in a plurality of votes corresponding to a plurality of adjacent samples, and adjusting the sampling phase when the running difference reaches a threshold.
摘要翻译：公开了在通信网络中提供时钟再同步的方法和装置。本文公开的时钟重新同步的示例性方法包括基于在采样数据流中的单个位间隔内发生的相邻采样来确定投票，其中当相邻采样指示采样时钟的采样相位为早期相对时，投票包括早期投票到所述比特间隔中的中心位置，并且其中所述投票包括晚期投票，当相邻样本指示所述采样阶段相对于所述中心位置较晚时，跟踪多个早期投票与多个晚期投票数之间的差异的投票对应于多个相邻样本，并且当运行差达到阈值时调整采样相位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式