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1. 发明授权

US09105660B2 Fin-FET and method of forming the same 有权
标题翻译： Fin-FET及其形成方法
公开(公告)号：US09105660B2
公开(公告)日：2015-08-11
申请号：US13211334
申请日：2011-08-17
申请人： Chen-Hua Tsai , Rai-Min Huang , Sheng-Huei Dai , Chun-Hsien Lin
发明人： Chen-Hua Tsai , Rai-Min Huang , Sheng-Huei Dai , Chun-Hsien Lin
IPC分类号： H01L29/66 , H01L21/02 , H01L21/20 , H01L29/78
CPC分类号： H01L29/7853 , H01L21/02647 , H01L21/2022 , H01L29/1054 , H01L29/16 , H01L29/66795 , H01L29/7842 , H01L29/785 , H01L2029/7858
摘要： A method of forming a Fin-FET is provided. A substrate is provided, then a mask layer is formed thereabove. A first trench is formed in the substrate and the mask layer. A semiconductor layer is formed in the first trench. Next, the mask layer is removed such that the semi-conductive layer becomes a fin structure embedded in the substrate and protruded above the substrate. Finally, a gate layer is formed on the fin structure.
摘要翻译：提供了形成Fin-FET的方法。提供衬底，然后在其上形成掩模层。在衬底和掩模层中形成第一沟槽。在第一沟槽中形成半导体层。接下来，去除掩模层，使得半导体层变成嵌入在衬底中并突出在衬底上的散热片结构。最后，在鳍结构上形成栅极层。

2. 发明授权

US09006092B2 Semiconductor structure having fluoride metal layer and process thereof 有权
标题翻译：具有氟化物金属层的半导体结构及其工艺
公开(公告)号：US09006092B2
公开(公告)日：2015-04-14
申请号：US13288041
申请日：2011-11-03
申请人： Kun-Hsien Lin , Chun-Hsien Lin , Hsin-Fu Huang
发明人： Kun-Hsien Lin , Chun-Hsien Lin , Hsin-Fu Huang
IPC分类号： H01L21/02 , H01L21/3205 , H01L21/8238 , H01L21/28 , H01L29/49 , H01L29/66 , H01L21/265 , H01L29/51
CPC分类号： H01L21/823842 , H01L21/265 , H01L21/28088 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A semiconductor structure includes a substrate, a dielectric layer and a fluoride metal layer. The dielectric layer is located on the substrate. The fluoride metal layer is located on the dielectric layer. Furthermore, the present invention also provides a semiconductor process to form said semiconductor structure.
摘要翻译：半导体结构包括基板，电介质层和氟化物金属层。电介质层位于衬底上。氟化金属层位于电介质层上。此外，本发明还提供了形成所述半导体结构的半导体工艺。

3. 发明授权

US08980753B2 Metal gate transistor and method for fabricating the same 有权
标题翻译：金属栅极晶体管及其制造方法
公开(公告)号：US08980753B2
公开(公告)日：2015-03-17
申请号：US12886580
申请日：2010-09-21
申请人： Yeng-Peng Wang , Chun-Hsien Lin , Chiu-Hsien Yeh , Chin-Cheng Chien , Chan-Lon Yang
发明人： Yeng-Peng Wang , Chun-Hsien Lin , Chiu-Hsien Yeh , Chin-Cheng Chien , Chan-Lon Yang
IPC分类号： H01L21/311 , H01L21/302 , H01L21/461 , C03C15/00 , C03C25/68 , C23F1/00 , B44C1/22 , H01L21/8238
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823814
摘要： A method for fabricating a metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a first transistor region and a second transistor region; forming a first metal-oxide semiconductor (MOS) transistor on the first transistor region and a second MOS transistor on the second transistor region, in which the first MOS transistor includes a first dummy gate and the second MOS transistor comprises a second dummy gate; forming a patterned hard mask on the second MOS transistor, in which the hard mask includes at least one metal atom; and using the patterned hard mask to remove the first dummy gate of the first MOS transistor.
摘要翻译：公开了一种用于制造金属栅极晶体管的方法。该方法包括以下步骤：提供具有第一晶体管区域和第二晶体管区域的衬底; 在第一晶体管区域上形成第一金属氧化物半导体（MOS）晶体管，在第二晶体管区域形成第二MOS晶体管，其中第一MOS晶体管包括第一虚拟栅极，第二MOS晶体管包括第二虚拟栅极; 在所述第二MOS晶体管上形成图案化的硬掩模，其中所述硬掩模包括至少一个金属原子; 以及使用图案化的硬掩模去除第一MOS晶体管的第一伪栅极。

4. 发明授权

US08805630B2 Method and system for modeling in semiconductor fabrication 有权
标题翻译：半导体制造中的建模方法和系统
公开(公告)号：US08805630B2
公开(公告)日：2014-08-12
申请号：US12546860
申请日：2009-08-25
申请人： Chun-Hsien Lin
发明人： Chun-Hsien Lin
IPC分类号： G01N37/00 , G06F19/00 , H01L21/66
CPC分类号： H01L22/20 , H01L22/12
摘要： A method for use in semiconductor fabrication is provided that includes providing manufacturing data of a semiconductor process, providing a plurality of functional transformations, optimizing each of the functional transformations based on the manufacturing data, selecting one of the functional transformations that has a least deviation with respect to the manufacturing data, predicting performance of the semiconductor process using the selected transformation function, and controlling a fabrication tool based on the predicted performance.
摘要翻译：提供了一种用于半导体制造的方法，其包括提供半导体工艺的制造数据，提供多个功能变换，基于制造数据优化每个功能变换，选择具有最小偏差的功能变换之一使用所选择的变换函数预测半导体处理的性能，并且基于预测的性能来控制制造工具。

5. 发明授权

US08664060B2 Semiconductor structure and method of fabricating the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08664060B2
公开(公告)日：2014-03-04
申请号：US13367382
申请日：2012-02-07
申请人： An-Chi Liu , Chun-Hsien Lin , Yu-Cheng Tung , Chien-Ting Lin , Wen-Tai Chiang , Shih-Hung Tsai , Ssu-I Fu , Ying-Tsung Chen , Chih-Wei Chen
发明人： An-Chi Liu , Chun-Hsien Lin , Yu-Cheng Tung , Chien-Ting Lin , Wen-Tai Chiang , Shih-Hung Tsai , Ssu-I Fu , Ying-Tsung Chen , Chih-Wei Chen
IPC分类号： H01L29/78
CPC分类号： H01L29/7834 , H01L29/66795 , H01L29/785 , H01L29/78654
摘要： A semiconductor structure and a method of fabricating the same comprising the steps of providing a substrate, forming at least one fin structure on said substrate, forming a gate covering said fin structure, forming a plurality of epitaxial structures covering said fin structures, performing a gate pullback process to reduce the critical dimension (CD) of said gate and separate said gate and said epitaxial structures, forming lightly doped drains (LDD) in said fin structures, and forming a spacer on said gate and said fin structures.
摘要翻译：一种半导体结构及其制造方法，包括以下步骤：提供衬底，在所述衬底上形成至少一个鳍结构，形成覆盖所述鳍结构的栅极，形成覆盖所述鳍结构的多个外延结构，拉回过程以减小所述栅极的临界尺寸（CD）并分离所述栅极和所述外延结构，在所述鳍结构中形成轻掺杂的漏极（LDD），以及在所述栅极和所述鳍结构上形成间隔物。

6. 发明授权

US08574990B2 Method of manufacturing semiconductor device having metal gate 有权
标题翻译：制造具有金属栅极的半导体器件的方法
公开(公告)号：US08574990B2
公开(公告)日：2013-11-05
申请号：US13033616
申请日：2011-02-24
申请人： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Shui-Yen Lu , Pei-Yu Chou , Shin-Chi Chen , Jiunn-Hsiung Liao , Shang-Yuan Tsai , Chan-Lon Yang , Teng-Chun Tsai , Chun-Hsien Lin
发明人： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Shui-Yen Lu , Pei-Yu Chou , Shin-Chi Chen , Jiunn-Hsiung Liao , Shang-Yuan Tsai , Chan-Lon Yang , Teng-Chun Tsai , Chun-Hsien Lin
IPC分类号： H01L21/00
CPC分类号： H01L29/66545 , H01L21/82345 , H01L21/823842 , H01L29/4966
摘要： The present invention provides a method of manufacturing semiconductor device having metal gate. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench and then a first metal layer and a first material layer are formed in the first trench. Next, the first metal layer and the first material layer are flattened. The second sacrifice gate is removed to form a second trench and then a second metal layer and a second material layer are formed in the second trench. Lastly, the second metal layer and the second material layer are flattened.
摘要翻译：本发明提供一种制造具有金属栅极的半导体器件的方法。首先，提供基板。具有第一牺牲栅极的第一导电型晶体管和具有第二牺牲栅极的第二导电型晶体管设置在衬底上。去除第一牺牲栅极以形成第一沟槽，然后在第一沟槽中形成第一金属层和第一材料层。接下来，第一金属层和第一材料层变平。去除第二牺牲栅极以形成第二沟槽，然后在第二沟槽中形成第二金属层和第二材料层。最后，第二金属层和第二材料层变平。

7. 发明授权

US08546202B2 Manufacturing method for semiconductor structures 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US08546202B2
公开(公告)日：2013-10-01
申请号：US13293090
申请日：2011-11-09
申请人： Yu-Cheng Tung , Chun-Hsien Lin
发明人： Yu-Cheng Tung , Chun-Hsien Lin
IPC分类号： H01L21/00
CPC分类号： H01L21/823431 , H01L21/3086 , H01L21/845
摘要： A manufacturing method for semiconductor structures includes providing a substrate having a first region and a second region defined thereon, forming a plurality of first patterns in the first region and at least a second pattern in the second region, forming a plurality of first spacers respectively on sidewalls of the first patterns and at least a second spacer on a sidewall of the second pattern, forming a patterned protecting layer in the second region, removing the first patterns from the first region to form a plurality of first masking patterns in the first region and at least a second masking pattern in the second region, and transferring the first masking patterns and the second masking pattern to the substrate.
摘要翻译：一种用于半导体结构的制造方法，包括：提供具有限定在其上的第一区域和第二区域的基板，在所述第一区域中形成多个第一图案，并且在所述第二区域中形成至少第二图案，分别在所述第一图案的侧壁和所述第二图案的侧壁上的至少第二间隔物在所述第二区域中形成图案化的保护层，从所述第一区域去除所述第一图案以在所述第一区域中形成多个第一掩蔽图案，以及在所述第二区域中的至少第二掩模图案，以及将所述第一掩模图案和所述第二掩模图案传送到所述基板。

8. 发明授权

US08496248B2 Printer with bracket for holding paper tray 失效
标题翻译：带支架的打印机，用于保持纸盘
公开(公告)号：US08496248B2
公开(公告)日：2013-07-30
申请号：US12755061
申请日：2010-04-06
申请人： Chen-Lu Fan , Chih-Kun Shih , Chun-Hsien Lin
发明人： Chen-Lu Fan , Chih-Kun Shih , Chun-Hsien Lin
IPC分类号： B65H39/10
CPC分类号： B41J29/02 , B65H31/24 , B65H2402/515 , B65H2402/5155 , B65H2402/64 , B65H2404/611 , B65H2405/332 , B65H2511/182 , B65H2511/20 , B65H2801/06 , B65H2220/02 , B65H2220/04 , B65H2220/11
摘要： A printer includes a main body capable of printing and outputting paper, a bracket attached to the main body, two sliding blocks, and a tray configured for receiving the paper. The bracket includes two sidewalls. A retaining member is secured to each sidewall. The sliding blocks are slidably attached to the sidewalls of the bracket. The tray is received in the bracket and has tray posts corresponding to the retaining members. The sliding blocks bring the tray to slide in the bracket. The retaining members have a first position, where the tray posts urge the retaining members to slide before passing across the retaining members, and a second position, where the tray posts are blocked by the retaining member when the tray is released from the sliding blocks.
摘要翻译：打印机包括能够打印和输出纸张的主体，附接到主体的支架，两个滑动块和被配置为接收纸张的托盘。支架包括两个侧壁。保持构件固定到每个侧壁。滑块可滑动地附接到支架的侧壁。托盘被容纳在托架中并且具有对应于保持构件的托盘柱。滑块使托盘在支架中滑动。保持构件具有第一位置，其中托盘支柱促使保持构件在穿过保持构件之前滑动，并且第二位置，当托盘从滑动块释放时，托架柱被保持构件阻挡。

9. 发明授权

US08477006B2 Resistor and manufacturing method thereof 有权
标题翻译：电阻及其制造方法
公开(公告)号：US08477006B2
公开(公告)日：2013-07-02
申请号：US13220721
申请日：2011-08-30
申请人： Jie-Ning Yang , Shih-Chieh Hsu , Chun-Hsien Lin , Yao-Chang Wang , Chi-Horn Pai , Chi-Sheng Tseng
发明人： Jie-Ning Yang , Shih-Chieh Hsu , Chun-Hsien Lin , Yao-Chang Wang , Chi-Horn Pai , Chi-Sheng Tseng
IPC分类号： H01C1/012
CPC分类号： H01L28/20 , H01L27/0629 , H01L29/66545
摘要： A manufacturing method for a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, respectively forming a transistor having a dummy gate in the transistor region and a resistor in the resistor region, removing the dummy gate and portions of the resistor to form a first trench in the transistor and two second trenches in the resistor, forming at least a high-k gate dielectric layer in the first trench and the second trenches, and forming a metal gate in the first trench and metal structures respectively in the second trenches.
摘要翻译：一种与具有金属栅极的晶体管集成的电阻器的制造方法，包括：提供具有晶体管区域和限定在其上的电阻器区域的衬底，分别形成晶体管区域中具有伪栅极的晶体管和电阻器区域中的电阻器，虚拟栅极和电阻器的部分，以在晶体管中形成第一沟槽，并且在电阻器中形成两个第二沟槽，在第一沟槽和第二沟槽中形成至少一个高k栅介质层，并在第一沟槽和第二沟槽中形成金属栅极沟槽和金属结构分别在第二沟槽。

10. 发明申请

US20130049924A1 RESISTOR AND MANUFACTURING METHOD THEREOF 有权
标题翻译：电阻及其制造方法
公开(公告)号：US20130049924A1
公开(公告)日：2013-02-28
申请号：US13220721
申请日：2011-08-30
申请人： Jie-Ning Yang , Shih-Chieh Hsu , Chun-Hsien Lin , Yao-Chang Wang , Chi-Horn Pai , Chi-Sheng Tseng
发明人： Jie-Ning Yang , Shih-Chieh Hsu , Chun-Hsien Lin , Yao-Chang Wang , Chi-Horn Pai , Chi-Sheng Tseng
IPC分类号： H01C7/00 , H01L21/02
CPC分类号： H01L28/20 , H01L27/0629 , H01L29/66545
摘要： A manufacturing method for a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, respectively forming a transistor having a dummy gate in the transistor region and a resistor in the resistor region, removing the dummy gate and portions of the resistor to form a first trench in the transistor and two second trenches in the resistor, forming at least a high-k gate dielectric layer in the first trench and the second trenches, and forming a metal gate in the first trench and metal structures respectively in the second trenches.
摘要翻译：一种与具有金属栅极的晶体管集成的电阻器的制造方法，包括：提供具有晶体管区域和限定在其上的电阻器区域的衬底，分别形成晶体管区域中具有伪栅极的晶体管和电阻器区域中的电阻器，虚拟栅极和电阻器的部分，以在晶体管中形成第一沟槽，并且在电阻器中形成两个第二沟槽，在第一沟槽和第二沟槽中形成至少一个高k栅介质层，并在第一沟槽和第二沟槽中形成金属栅极沟槽和金属结构分别在第二沟槽。

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