专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07273789B2 Method of fabricating heterojunction bipolar transistor 有权
标题翻译：异质结双极晶体管的制造方法
公开(公告)号：US07273789B2
公开(公告)日：2007-09-25
申请号：US11227503
申请日：2005-09-15
申请人： Byoung Gue Min , Jong Min Lee , Seong Il Kim , Chul Won Ju , Kyung Ho Lee
发明人： Byoung Gue Min , Jong Min Lee , Seong Il Kim , Chul Won Ju , Kyung Ho Lee
IPC分类号： H01L21/331
CPC分类号： H01L29/66318 , H01L29/7371
摘要： Provided is a method of fabricating a heterojunction bipolar transistor (HBT). The method includes: sequentially depositing a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter capping layer on a substrate; forming an emitter electrode on the emitter capping layer; forming a mesa type emitter to expose the base layer by sequentially etching the emitter capping layer and the emitter layer using the emitter electrode as an etch mask in vertical and negative-sloped directions to the substrate, respectively; and forming a base electrode on the exposed base layer using the emitter electrode as a mask in self-alignment with the emitter electrode. In this method, a distance between the mesa type emitter and the base electrode can be minimized and reproducibly controlled. Also, a self-aligned device with an excellent high-frequency characteristic can be embodied.
摘要翻译：提供了一种制造异质结双极晶体管（HBT）的方法。该方法包括：在衬底上依次沉积副集电极层，集电极层，基极层，发射极层和发射极覆盖层; 在发射极盖层上形成发射电极; 通过使用发射极电极作为蚀刻掩模，分别在垂直和负向倾斜的方向上依次蚀刻发射极覆盖层和发射极层来形成台面型发射极以暴露基底层; 以及使用发射电极作为与发射极电极自对准的掩模，在所述暴露的基底层上形成基极。在这种方法中，台面型发射极和基极之间的距离可以被最小化并可重复地控制。此外，可以实现具有优异的高频特性的自对准装置。

2. 发明授权

US07364977B2 Heterojunction bipolar transistor and method of fabricating the same 失效
标题翻译：异质结双极晶体管及其制造方法
公开(公告)号：US07364977B2
公开(公告)日：2008-04-29
申请号：US10857655
申请日：2004-05-28
申请人： Byoung-Gue Min , Kyung-Ho Lee , Seong-Il Kim , Jong-Min Lee , Chul-Won Ju
发明人： Byoung-Gue Min , Kyung-Ho Lee , Seong-Il Kim , Jong-Min Lee , Chul-Won Ju
IPC分类号： H01L21/8222
CPC分类号： H01L29/66318 , H01L29/7371
摘要： Disclosed are a heterojunction bipolar transistor and a method of fabricating the same. A first dielectric layer easily etched is deposited on the overall surface of a substrate before an isolation region is defined. The first dielectric layer and a sub-collector layer are selectively etched, and then a second dielectric layer etched at a low etch rate is deposited on the overall surface of the substrate. Via holes are formed in the first and second dielectric layers, and then the first dielectric layer is removed using a difference between etch characteristics of the first and second dielectric layers. Accordingly, a reduction in power gain, generated at the interface of a compound semiconductor and a dielectric insulating layer (the second dielectric layer), can be eliminated.
摘要翻译：公开了异质结双极晶体管及其制造方法。在限定隔离区之前，易于蚀刻的第一电介质层沉积在基板的整个表面上。选择性地蚀刻第一介电层和次集电极层，然后以低蚀刻速率蚀刻的第二电介质层沉积在基板的整个表面上。在第一和第二电介质层中形成通孔，然后使用第一和第二电介质层的蚀刻特性之间的差异去除第一介电层。因此，可以消除在化合物半导体和介电绝缘层（第二介电层）的界面处产生的功率增益的降低。

3. 发明申请

US20050133820A1 Heterojunction bipolar transistor and method of fabricating the same 失效
标题翻译：异质结双极晶体管及其制造方法
公开(公告)号：US20050133820A1
公开(公告)日：2005-06-23
申请号：US10857655
申请日：2004-05-28
申请人： Byoung-Gue Min , Kyung-Ho Lee , Seong-Il Kim , Jong-Min Lee , Chul-Won Ju
发明人： Byoung-Gue Min , Kyung-Ho Lee , Seong-Il Kim , Jong-Min Lee , Chul-Won Ju
IPC分类号： H01L21/331 , H01L29/737 , H01L29/739 , H01L21/8222 , H01L31/0328
CPC分类号： H01L29/66318 , H01L29/7371
摘要： Disclosed are a heterojunction bipolar transistor and a method of fabricating the same. A first dielectric layer easily etched is deposited on the overall surface of a substrate before an isolation region is defined. The first dielectric layer and a sub-collector layer are selectively etched, and then a second dielectric layer etched at a low etch rate is deposited on the overall surface of the substrate. Via holes are formed in the first and second dielectric layers, and then the first dielectric layer is removed using a difference between etch characteristics of the first and second dielectric layers. Accordingly, a reduction in power gain, generated at the interface of a compound semiconductor and a dielectric insulating layer (the second dielectric layer), can be eliminated.
摘要翻译：公开了异质结双极晶体管及其制造方法。在限定隔离区之前，易于蚀刻的第一电介质层沉积在基板的整个表面上。选择性地蚀刻第一介电层和次集电极层，然后以低蚀刻速率蚀刻的第二电介质层沉积在基板的整个表面上。在第一和第二电介质层中形成通孔，然后使用第一和第二电介质层的蚀刻特性之间的差异去除第一介电层。因此，可以消除在化合物半导体和介电绝缘层（第二介电层）的界面处产生的功率增益的降低。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式