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1. 实用新型

TWM516048U 一種具有矽氧烷互穿網奈米胺微粒層之常溫速乾表面改質劑複合結構體失效
简体标题：一种具有硅氧烷互穿网奈米胺微粒层之常温速干表面改质剂复合结构体
公开(公告)号：TWM516048U
公开(公告)日：2016-01-21
申请号：TW103220398
申请日：2014-11-17
申请人：黃慶成 , CHING CHENG HUANG
发明人：洪壽懋 , 黃慶成 , HUANG, CHING CHENG , 李美婷 , LEE, MEI TING
IPC分类号： C23C22/05

2. 发明授权

US08901733B2 Reliable metal bumps on top of I/O pads after removal of test probe marks 有权
标题翻译：移除测试探针后，I / O焊盘顶部可靠的金属凸块
公开(公告)号：US08901733B2
公开(公告)日：2014-12-02
申请号：US12182145
申请日：2008-07-30
申请人： Ching-Cheng Huang , Chuen-Jye Lin , Ming-Ta Lei , Mou-Shiung Lin
发明人： Ching-Cheng Huang , Chuen-Jye Lin , Ming-Ta Lei , Mou-Shiung Lin
IPC分类号： H01L23/48 , H01L23/00 , H01L23/31
CPC分类号： H01L24/05 , H01L23/3192 , H01L24/03 , H01L24/11 , H01L24/12 , H01L2224/02166 , H01L2224/03912 , H01L2224/0401 , H01L2224/05016 , H01L2224/05018 , H01L2224/05019 , H01L2224/05027 , H01L2224/05093 , H01L2224/05552 , H01L2224/05556 , H01L2224/05558 , H01L2224/05562 , H01L2224/05572 , H01L2224/1147 , H01L2224/11901 , H01L2224/13006 , H01L2224/13022 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2924/00012
摘要： In accordance with the objectives of the invention a new method is provided for the creation of metal bumps over surfaces of I/O pads. Contact pads are provided over the surface of a layer of dielectric. The aluminum of the I/O pads, which have been used as I/O pads during wafer level semiconductor device testing, is completely or partially removed over a surface area that is smaller than the surface area of the contact pad using methods of metal dry etching or wet etching. The contact pad can be accessed either by interconnect metal created in a plane of the contact pad or by via that are provided through the layer of dielectric over which the contact pad has been deposited. The process can be further extended by the deposition, patterning and etching of a layer of polyimide over the layer of passivation that serves to protect the contact pad.
摘要翻译：根据本发明的目的，提供了一种在I / O焊盘的表面上形成金属凸块的新方法。接触垫设置在电介质层的表面上。在晶片级半导体器件测试期间用作I / O焊盘的I / O焊盘的铝在使用金属干燥的方法的表面积小于接触焊盘的表面积的情况下被完全或部分去除蚀刻或湿蚀刻。接触焊盘可以通过在接触焊盘的平面中产生的互连金属或通过已经沉积接触焊盘的电介质层提供的通孔来访问。通过在用于保护接触焊盘的钝化层上的聚酰亚胺层的沉积，图案化和蚀刻可以进一步扩展该工艺。

3. 发明授权

US08426982B2 Structure and manufacturing method of chip scale package 有权
公开(公告)号：US08426982B2
公开(公告)日：2013-04-23
申请号：US12512073
申请日：2009-07-30
申请人： Jin-Yuan Lee , Ching-Cheng Huang , Mou-Shiung Lin
发明人： Jin-Yuan Lee , Ching-Cheng Huang , Mou-Shiung Lin
IPC分类号： H01L23/02 , H01L23/48
CPC分类号： H01L23/293 , H01L23/3114 , H01L23/49827 , H01L24/10 , H01L24/13 , H01L24/48 , H01L24/81 , H01L2224/05124 , H01L2224/05155 , H01L2224/05599 , H01L2224/05647 , H01L2224/13 , H01L2224/13099 , H01L2224/13111 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/81801 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure.

4. 发明授权

US08211791B2 Method for fabricating circuitry component 有权
标题翻译：电路元件制造方法
公开(公告)号：US08211791B2
公开(公告)日：2012-07-03
申请号：US10382699
申请日：2003-03-05
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76838 , H01L21/768 , H01L21/76807 , H01L23/5286 , H01L23/5329 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.
摘要翻译：芯片结构包括基板，第一堆叠层，钝化层和第二堆积层。基板包括放置在基板的表面上的许多电气装置。第一组合层位于基底上。第一组合层设置有第一电介质体和第一互连方案，其中第一互连方案与第一介电体内部交错并电连接到电气装置。第一互连方案由第一金属层和插塞构成，其中相邻的第一金属层通过插塞电连接。钝化层设置在第一堆叠层上并且设有暴露第一互连方案的开口。第二堆叠层形成在钝化层上。第二组合层设置有第二电介质体和第二互连方案，其中第二互连方案在第二介电体内部交织并与第一互连方案电连接。第二互连方案由至少一个第二金属层和至少一个通孔金属填料构成，其中第二金属层电连接到通孔金属填料。第二金属层的迹线的厚度，宽度和横截面积分别大于第一金属层的厚度，宽度和横截面面积。

5. 发明申请

US20110205720A1 INTEGRATED CHIP PACKAGE STRUCTURE USING ORGANIC SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：使用有机基板的集成芯片包装结构及其制造方法
公开(公告)号：US20110205720A1
公开(公告)日：2011-08-25
申请号：US13031163
申请日：2011-02-18
申请人： Jin-Yuan Lee , Mou-Shiung Lin , Ching-Cheng Huang
发明人： Jin-Yuan Lee , Mou-Shiung Lin , Ching-Cheng Huang
IPC分类号： H05K7/00
CPC分类号： H01L21/6835 , H01L21/4857 , H01L23/49822 , H01L23/5389 , H01L24/19 , H01L24/97 , H01L2221/68363 , H01L2221/68377 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/211 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1461 , H01L2924/15311 , H01L2924/15788 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , Y10T29/5313 , Y10T29/5317 , H01L2224/82 , H01L2224/83 , H01L2924/00
摘要： An integrated chip package structure and method of manufacturing the same is by adhering dies on an organic substrate and forming a thin-film circuit layer on top of the dies and the organic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.
摘要翻译：集成芯片封装结构及其制造方法是通过在有机基板上附着模具并在模具和有机基板的顶部形成薄膜电路层。其中薄膜电路层具有电连接到模具的金属焊盘的外部电路，其延伸到模具的有效表面外部的区域，以扇出模具的金属焊盘。此外，多个有源器件和内部电路位于管芯的有效表面上。有源器件的信号通过内部电路传输到外部电路，并通过内部电路从外部电路传输回其他有源器件。此外，芯片封装结构允许将具有不同功能的多个裸片封装在集成封装中并通过外部电路电连接裸片。

6. 发明授权

US07977763B2 Chip package with die and substrate 有权
标题翻译：芯片封装，带芯片和基板
公开(公告)号：US07977763B2
公开(公告)日：2011-07-12
申请号：US10996537
申请日：2004-11-24
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
IPC分类号： H01L23/58 , H05K7/00
CPC分类号： H01L24/19 , H01L21/6835 , H01L23/3114 , H01L23/5389 , H01L24/97 , H01L2221/68377 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/211 , H01L2224/32225 , H01L2224/73267 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15311 , H01L2924/15788 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3011 , H01L2224/82 , H01L2924/00 , H01L2224/83
摘要： A thin film semiconductor die circuit package is provided utilizing low dielectric constant (k) polymer material for the insulating layers of the metal interconnect structure. Five embodiments include utilizing glass, glass-metal composite, and glass/glass sandwiched substrates. The substrates form the base for mounting semiconductor dies and fabricating the thin film interconnect structure.
摘要翻译：使用用于金属互连结构的绝缘层的低介电常数（k）聚合物材料来提供薄膜半导体管芯电路封装。五个实施方案包括利用玻璃，玻璃 - 金属复合材料和玻璃/玻璃夹层基材。基板形成用于安装半导体管芯的基座并制造薄膜互连结构。

7. 发明授权

US07915157B2 Chip structure and process for forming the same 有权
公开(公告)号：US07915157B2
公开(公告)日：2011-03-29
申请号：US12025001
申请日：2008-02-02
申请人： Jin-Yuan Lee , Mou-Shiung Lin , Ching-Cheng Huang
发明人： Jin-Yuan Lee , Mou-Shiung Lin , Ching-Cheng Huang
IPC分类号： H01L21/44
CPC分类号： H01L28/10 , H01L21/768 , H01L21/76807 , H01L21/76838 , H01L23/522 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/60 , H01L24/02 , H01L24/10 , H01L24/11 , H01L24/13 , H01L27/0251 , H01L27/0676 , H01L27/08 , H01L28/20 , H01L2224/0231 , H01L2224/02311 , H01L2224/02313 , H01L2224/0401 , H01L2224/13 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/04953 , H01L2924/12044 , H01L2924/14 , H01L2924/15174 , H01L2924/19041 , H01L2924/30105 , Y10T29/49124 , Y10T29/49204 , H01L2924/00
摘要： A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

8. 发明授权

US07728090B2 Norbornene compounds with cross-linkable groups and their derivatives 有权
标题翻译：具有可交联基团的降冰片烯化合物及其衍生物
公开(公告)号：US07728090B2
公开(公告)日：2010-06-01
申请号：US11522331
申请日：2006-09-18
申请人： Der-Jang Liaw , Ching-Cheng Huang , Shou-Mau Hong , Ming-Hung Huang
发明人： Der-Jang Liaw , Ching-Cheng Huang , Shou-Mau Hong , Ming-Hung Huang
IPC分类号： C08G61/08 , C07D303/04
CPC分类号： C08F232/08
摘要： The present invention provided a norbornene compound with cross-linkable groups and their derivative polymers, wherein said cross-linkable groups were olefin or epoxy groups. Norbornene polymers with cross-linkable side chain and their block copolymers as well as modified derivatives were prepared via living ring-open metathesis polymerization method. The resulting polymers with excellent solubility and optic properties had narrow molecular weight distribution, well-controlled molecular weight, small refraction ration and high transparency. They were also suitable for preparing hybrid materials with high thermal stability and chemical resistance.
摘要翻译：本发明提供了具有可交联基团的降冰片烯化合物及其衍生聚合物，其中所述可交联基团是烯烃或环氧基团。通过活性开环复分解法制备具有可交联侧链的降冰片烯聚合物及其嵌段共聚物以及改性衍生物。所得聚合物具有优异的溶解度和光学性能，分子量分布窄，分子量控制小，折射率小，透明度高。它们也适用于制备具有高热稳定性和耐化学性的混合材料。

9. 发明授权

US07498196B2 Structure and manufacturing method of chip scale package 有权
标题翻译：芯片级封装的结构和制造方法
公开(公告)号：US07498196B2
公开(公告)日：2009-03-03
申请号：US09821546
申请日：2001-03-30
申请人： Jin-Yuan Lee , Ching-Cheng Huang , Mou-Shiung Lin
发明人： Jin-Yuan Lee , Ching-Cheng Huang , Mou-Shiung Lin
IPC分类号： H01L21/44 , H01L21/48
CPC分类号： H01L23/293 , H01L23/3114 , H01L23/49827 , H01L24/10 , H01L24/13 , H01L24/48 , H01L24/81 , H01L2224/05124 , H01L2224/05155 , H01L2224/05599 , H01L2224/05647 , H01L2224/13 , H01L2224/13099 , H01L2224/13111 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/81801 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure.
摘要翻译：公开了一种芯片级封装（CSP）及其形成方法。首先将不具有常规球形安装件的单个芯片附接到具有与单个芯片上的输入/输出（I / O）焊盘相对应的开口的粘合剂基底（布线基板）复合材料，以形成复合芯片封装。然后在开口上执行球安装，从而将芯片位置处的I / O焊盘直接连接到下一级封装。在另一个实施例中，首先在晶片侧形成粘合剂层以形成等离子体，然后在CSP中将其锯切。然后将已经在其上的粘合剂的CSP粘合到基底上。复合芯片封装可以可选地用模制材料封装。 CSP提供集成和更短的芯片连接，特别适用于高频电路应用，并可以利用当前现有的测试基础架构。

10. 发明申请

US20090053287A1 POROUS DRESSING 审中-公开
标题翻译：多孔连接
公开(公告)号：US20090053287A1
公开(公告)日：2009-02-26
申请号：US11926575
申请日：2007-10-29
申请人： Ching-Cheng HUANG , Quang-Wei CHANG , Yung-Sheng LIN , Ting-Kai LEUNG
发明人： Ching-Cheng HUANG , Quang-Wei CHANG , Yung-Sheng LIN , Ting-Kai LEUNG
IPC分类号： A61L15/00
CPC分类号： A61L15/44 , A61L15/20 , A61L15/425 , A61L2300/41
摘要： A porous dressing is provided. The porous dressing includes a polymeric layer, a pharmaceutically active ingredient and a metal oxide. The polymeric layer has a porosity and a bio-compatibility, and the pharmaceutically active ingredient and the metal oxide distribute in one selected from a group consisting of in the polymeric layer, on a surface of the polymeric layer and a combination thereof.
摘要翻译：提供多孔敷料。多孔敷料包括聚合物层，药物活性成分和金属氧化物。聚合物层具有孔隙率和生物相容性，并且药物活性成分和金属氧化物分布在聚合物层中的聚合物层，聚合物层的表面及其组合中的一个中。

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