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1. 发明授权

US06953715B2 Method of controlling a capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor 有权
公开(公告)号：US06953715B2
公开(公告)日：2005-10-11
申请号：US10934014
申请日：2004-09-03
申请人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
发明人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
IPC分类号： G02F1/1362 , H01L21/77 , H01L21/84 , H01L27/12 , H01L27/13 , H01L29/423 , H01L21/00
CPC分类号： H01L27/1248 , G02F1/136213 , H01L27/1255 , H01L29/42384
摘要： A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming an undoped amorphous silicon layer on a silicon nitride layer, ii) forming an etching mask on the undoped amorphous silicon layer, and iii) forming two doped amorphous silicon layers on portion of the undoped amorphous silicon layer and the etching mask, the two doped amorphous silicon layers being spaced apart and located on either side of the gate, wherein an etching selectivity ratio of the undpoed and doped amorphous silicon layers over the dielectric layer being not less than about 5.0.

2. 发明授权

US06800510B2 Method of controlling storage capacitor's capacitance of thin film transistor liquid crystal display 有权
标题翻译：控制存储电容器薄膜晶体管液晶显示器电容的方法
公开(公告)号：US06800510B2
公开(公告)日：2004-10-05
申请号：US10289470
申请日：2002-11-06
申请人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
发明人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
IPC分类号： H01L2100
CPC分类号： H01L27/1248 , G02F1/136213 , H01L27/1255 , H01L29/42384
摘要： A method of controlling the capacitance of the TFT-LCD storage capacitor is provided. The gate dielectric layer of the TFT is composed of a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when a doped and an undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled; thereby the capacitance of the storage capacitor can be controlled.
摘要翻译：提供了一种控制TFT-LCD存储电容器的电容的方法。 TFT的栅介质层由氮化硅层，电介质层和氮化硅层组成，非晶硅层在电介质层上的蚀刻选择性不小于约5.0。因此，当蚀刻掺杂的和未掺杂的非晶硅层以形成源极/漏极堆叠层时或者蚀刻导电层以在栅极介电层上形成栅极时，介电层可以是蚀刻停止层。因此，可以控制介电层厚度; 从而可以控制存储电容器的电容。

3. 发明授权

US07439544B2 Structure and manufacturing method of an image TFT array 有权
标题翻译：图像TFT阵列的结构和制造方法
公开(公告)号：US07439544B2
公开(公告)日：2008-10-21
申请号：US10907998
申请日：2005-04-25
申请人： Chin-Mao Lin , Kei-Hsiung Yang , Chian-Chih Hsiao
发明人： Chin-Mao Lin , Kei-Hsiung Yang , Chian-Chih Hsiao
IPC分类号： H01L27/14
CPC分类号： H01L27/14692 , H01L27/1255 , H01L27/1288 , H01L27/14658
摘要： The present invention provides a manufacturing method of an image TFT array, which includes providing a substrate including a thin film transistor region, a storage capacitor region, a pad region, and a common electrode region, forming a photoresist layer on the substrate, and performing a photolithographic and etching process by utilizing a half-tone mask to pattern the photoresist layer to define a position of a through hole on the storage capacitor region and form the photoresist layer of a first thickness on the thin film transistor region and the photoresist layer of a second thickness on the region between the thin film transistor region and the storage capacitor region, wherein the first thickness is greater than the second thickness.
摘要翻译：本发明提供了一种图像TFT阵列的制造方法，其包括提供包括薄膜晶体管区域，保持电容器区域，焊盘区域和公共电极区域的衬底，在衬底上形成光致抗蚀剂层，并且执行通过利用半色调掩模来对光致抗蚀剂层进行图案化以定义存储电容器区域上的通孔的位置并在薄膜晶体管区域和光致抗蚀剂层上形成第一厚度的光致抗蚀剂层的光刻和蚀刻工艺在薄膜晶体管区域和存储电容器区域之间的区域上的第二厚度，其中第一厚度大于第二厚度。

4. 发明授权

US07087469B2 Method of controlling a capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor 有权
标题翻译：控制薄膜晶体管液晶显示器（TFT-LCD）存储电容器的电容的方法
公开(公告)号：US07087469B2
公开(公告)日：2006-08-08
申请号：US10934242
申请日：2004-09-03
申请人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
发明人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
IPC分类号： H01L21/00
CPC分类号： H01L27/1248 , G02F1/136213 , H01L27/1255 , H01L29/42384
摘要： A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming a silicon island and a bottom electrode on the transparent substrate, the silicon island having an undoped region located on the central portion, and two doped regions respectively located on both sides, ii) forming a first silicon nitride layer on the transparent substrate, and iii) forming a stacked layer comprising a second silicon nitride layer and a conductive layer on the undoped region of the silicon island, and the first conductive layer of the stacked layer serving as a gate of a thin film transistor, wherein an etching selectivity ratio of the conductive layer over the dielectric layer is not less than about 5.0.
摘要翻译：公开了一种控制薄膜晶体管液晶显示器（TFT-LCD）存储电容器的电容的方法。在某些实施例中，该方法包括：i）在透明基底上形成硅岛和底部电极，硅岛具有位于中心部分上的未掺杂区域，以及分别位于两侧的两个掺杂区域，ii）形成第一氮化硅层，以及iii）在所述硅岛的未掺杂区域上形成包括第二氮化硅层和导电层的堆叠层，并且所述层叠层的第一导电层用作薄的栅极薄膜晶体管，其中导电层在电介质层上的蚀刻选择率不小于约5.0。

5. 发明授权

US07145172B2 Thin film transistor array substrate 有权
标题翻译：薄膜晶体管阵列基板
公开(公告)号：US07145172B2
公开(公告)日：2006-12-05
申请号：US10932828
申请日：2004-09-02
申请人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
发明人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
IPC分类号： H01L31/0376 , H01L21/00
CPC分类号： H01L27/1248 , G02F1/136213 , H01L27/1255 , H01L29/42384
摘要： A thin film transistor array substrate of a thin film transistor liquid crystal display (TFT-LCD) is provided. The gate dielectric layer of the TFT includes a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when doped and undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled, and thereby the capacitance of the storage capacitor can be controlled.
摘要翻译：提供薄膜晶体管液晶显示器（TFT-LCD）的薄膜晶体管阵列基板。 TFT的栅介质层包括氮化硅层，电介质层和氮化硅层，并且非晶硅层在电介质层上的蚀刻选择性不小于约5.0。因此，当掺杂和非掺杂非晶硅层被蚀刻以形成源极/漏极堆叠层时，介电层可以是蚀刻停止层，或蚀刻导电层以在栅极介电层上形成栅极。因此，可以控制介电层厚度，从而可以控制存储电容器的电容。

6. 发明申请

US20060183263A1 Structure and Manufacturing Method of An Image TFT Array 有权
标题翻译：图像TFT阵列的结构和制造方法
公开(公告)号：US20060183263A1
公开(公告)日：2006-08-17
申请号：US10907998
申请日：2005-04-25
申请人： Chin-Mao Lin , Kei-Hsiung YANG , Chian-Chih Hsiao
发明人： Chin-Mao Lin , Kei-Hsiung YANG , Chian-Chih Hsiao
IPC分类号： H01L21/00
CPC分类号： H01L27/14692 , H01L27/1255 , H01L27/1288 , H01L27/14658
摘要： The present invention provides a manufacturing method of an image TFT array, which includes providing a substrate including a thin film transistor region, a storage capacitor region, a pad region, and a common electrode region, forming a photoresist layer on the substrate, and performing a photolithographic and etching process by utilizing a half-tone mask to pattern the photoresist layer to define a position of a through hole on the storage capacitor region and form the photoresist layer of a first thickness on the thin film transistor region and the photoresist layer of a second thickness on the region between the thin film transistor region and the storage capacitor region, wherein the first thickness is greater than the second thickness.
摘要翻译：本发明提供了一种图像TFT阵列的制造方法，其包括提供包括薄膜晶体管区域，保持电容器区域，焊盘区域和公共电极区域的衬底，在衬底上形成光致抗蚀剂层，并且执行通过利用半色调掩模来对光致抗蚀剂层进行图案化以定义存储电容器区域上的通孔的位置并在薄膜晶体管区域和光致抗蚀剂层上形成第一厚度的光致抗蚀剂层的光刻和蚀刻工艺在薄膜晶体管区域和存储电容器区域之间的区域上的第二厚度，其中第一厚度大于第二厚度。

7. 发明申请

US20050037533A1 Method of controlling a capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor 有权
标题翻译：控制薄膜晶体管液晶显示器（TFT-LCD）存储电容器的电容的方法
公开(公告)号：US20050037533A1
公开(公告)日：2005-02-17
申请号：US10934014
申请日：2004-09-03
申请人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
发明人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
IPC分类号： G02F1/1362 , H01L21/77 , H01L21/84 , H01L27/12 , H01L27/13 , H01L29/423 , H01L21/00
CPC分类号： H01L27/1248 , G02F1/136213 , H01L27/1255 , H01L29/42384
摘要： A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming an undoped amorphous silicon layer on a silicon nitride layer, ii) forming an etching mask on the undoped amorphous silicon layer, and iii) forming two doped amorphous silicon layers on portion of the undoped amorphous silicon layer and the etching mask, the two doped amorphous silicon layers being spaced apart and located on either side of the gate, wherein an etching selectivity ratio of the undpoed and doped amorphous silicon layers over the dielectric layer being not less than about 5.0.
摘要翻译：公开了一种控制薄膜晶体管液晶显示器（TFT-LCD）存储电容器的电容的方法。在某些实施例中，该方法包括：i）在氮化硅层上形成未掺杂的非晶硅层，ii）在未掺杂的非晶硅层上形成蚀刻掩模，以及iii）在未掺杂的非晶硅的部分上形成两个掺杂非晶硅层层和蚀刻掩模，两个掺杂的非晶硅层间隔开并位于栅极的任一侧，其中在电介质层上的未掺杂和掺杂的非晶硅层的蚀刻选择率不小于约5.0。

8. 发明申请

US20050032263A1 Method of controlling a capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor 有权
标题翻译：控制薄膜晶体管液晶显示器（TFT-LCD）存储电容器的电容的方法
公开(公告)号：US20050032263A1
公开(公告)日：2005-02-10
申请号：US10934242
申请日：2004-09-03
申请人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
发明人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
IPC分类号： G02F1/1362 , H01L21/77 , H01L21/84 , H01L27/12 , H01L27/13 , H01L29/423 , H01L21/00
CPC分类号： H01L27/1248 , G02F1/136213 , H01L27/1255 , H01L29/42384
摘要： A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming a silicon island and a bottom electrode on the transparent substrate, the silicon island having an undoped region located on the central portion, and two doped regions respectively located on both sides, ii) forming a first silicon nitride layer on the transparent substrate, and iii) forming a stacked layer comprising a second silicon nitride layer and a conductive layer on the undoped region of the silicon island, and the first conductive layer of the stacked layer serving as a gate of a thin film transistor, wherein an etching selectivity ratio of the conductive layer over the dielectric layer is not less than about 5.0.
摘要翻译：公开了一种控制薄膜晶体管液晶显示器（TFT-LCD）存储电容器的电容的方法。在某些实施例中，该方法包括：i）在透明基底上形成硅岛和底部电极，硅岛具有位于中心部分上的未掺杂区域，以及分别位于两侧的两个掺杂区域，ii）形成第一氮化硅层，以及iii）在所述硅岛的未掺杂区域上形成包括第二氮化硅层和导电层的堆叠层，并且所述层叠层的第一导电层用作薄的栅极薄膜晶体管，其中导电层在电介质层上的蚀刻选择率不小于约5.0。

9. 发明申请

US20050023533A1 Thin film transistor array substrate 有权
标题翻译：薄膜晶体管阵列基板
公开(公告)号：US20050023533A1
公开(公告)日：2005-02-03
申请号：US10932828
申请日：2004-09-02
申请人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
发明人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
IPC分类号： G02F1/1362 , H01L21/77 , H01L21/84 , H01L27/12 , H01L27/13 , H01L29/423 , H01L29/04
CPC分类号： H01L27/1248 , G02F1/136213 , H01L27/1255 , H01L29/42384
摘要： A thin film transistor array substrate of a thin film transistor liquid crystal display (TFT-LCD) is provided. The gate dielectric layer of the TFT includes a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when doped and undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled, and thereby the capacitance of the storage capacitor can be controlled.
摘要翻译：提供薄膜晶体管液晶显示器（TFT-LCD）的薄膜晶体管阵列基板。 TFT的栅介质层包括氮化硅层，电介质层和氮化硅层，并且非晶硅层在电介质层上的蚀刻选择性不小于约5.0。因此，当掺杂和非掺杂非晶硅层被蚀刻以形成源极/漏极堆叠层时，介电层可以是蚀刻停止层，或蚀刻导电层以在栅极介电层上形成栅极。因此，可以控制介电层厚度，从而可以控制存储电容器的电容。

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