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1. 发明申请

US20120269308A1 SAMPLING CLOCK SELECTION MODULE OF SERIAL DATA STREAM 有权
标题翻译：串行数据流采样时钟选择模块
公开(公告)号：US20120269308A1
公开(公告)日：2012-10-25
申请号：US13448677
申请日：2012-04-17
申请人： REN-FENG HUANG , HUI WEN MIAO , KO-YANG TSO , CHIN-CHIEH CHAO
发明人： REN-FENG HUANG , HUI WEN MIAO , KO-YANG TSO , CHIN-CHIEH CHAO
IPC分类号： H04L7/027
CPC分类号： G06F13/4291 , H04L7/0004 , H04L7/0337 , H04L7/046
摘要： A sampling clock selection module for a serial data stream is disclosed. The sampling clock selection module includes a multi-phase generation circuit, a sampling circuit, a comparison unit and a logic operation unit. The multi-phase generation circuit generates a plurality of non-overlapping clock phases derived from a reference clock signal. The phase selection circuit selects a sampling clock phase under a calibration mode. The sampling circuit performs sampling on the serial data stream a plurality of times to generate a plurality of sampled values in response to the sampling clock phase. The comparison unit compares the sampled values with the serial data stream so as to update a plurality of flag signals. The logic operation unit performs a logic operation on the flag signals so as to select a sampling clock phase under a normal operation mode from the clock phases.
摘要翻译：公开了一种用于串行数据流的采样时钟选择模块。采样时钟选择模块包括多相产生电路，采样电路，比较单元和逻辑运算单元。多相产生电路产生从参考时钟信号导出的多个非重叠时钟相位。相位选择电路在校准模式下选择采样时钟相位。采样电路对串行数据流进行多次采样，以响应采样时钟相位产生多个采样值。比较单元将采样值与串行数据流进行比较，以更新多个标志信号。逻辑运算部对标志信号进行逻辑运算，从时钟相位选择正常工作模式下的采样时钟相位。

2. 发明授权

US07664219B2 Flip-flop and shift register 有权
标题翻译：触发器和移位寄存器
公开(公告)号：US07664219B2
公开(公告)日：2010-02-16
申请号：US12073197
申请日：2008-03-03
申请人： Ko-Yang Tso , Hui-Wen Miao , Chin-Chieh Chao
发明人： Ko-Yang Tso , Hui-Wen Miao , Chin-Chieh Chao
IPC分类号： G11C19/00
CPC分类号： H03K3/35625 , H03K3/356156
摘要： A flip-flop is provided. The flip-flop is used in a shift register in a source driver. The flip-flop is used to receive a first clock signal, an input signal and output an output signal. The output signal is fed back to the flip-flop. The flip-flop includes a flop core for receiving the input signal and output the output signal. When the input signal and the output signal are all disabled, the flop core is disabled to function. When the input signal or the output signal is enabled, the flop core is enabled to function to output the output signal.
摘要翻译：提供了一个触发器。触发器用于源驱动器中的移位寄存器。触发器用于接收第一时钟信号，输入信号并输出输出信号。输出信号反馈给触发器。触发器包括用于接收输入信号并输出输出信号的触发器芯。当输入信号和输出信号都被禁用时，触发器内核被禁用。当输入信号或输出信号被使能时，触发器使能使能输出输出信号。

3. 发明授权

US07656203B2 Receiving circuit and method thereof 有权
标题翻译：接收电路及其方法
公开(公告)号：US07656203B2
公开(公告)日：2010-02-02
申请号：US12073196
申请日：2008-03-03
申请人： Chih-Yu Lee , Yong-Nien Rao , Ko-Yang Tso , Hui-Wen Miao , Chin-Chieh Chao
发明人： Chih-Yu Lee , Yong-Nien Rao , Ko-Yang Tso , Hui-Wen Miao , Chin-Chieh Chao
IPC分类号： H03B1/00
CPC分类号： H04L25/0292 , H04L25/0272
摘要： A receiving circuit is provided for receiving a data signal and a clock signal, which are RSDS signals, and outputting an output data signal to a data driver. The receiving circuit includes a data comparator, a data intermediate circuit, a clock comparator, a clock intermediate, and a flip-flop. The data comparator, driven with a data bias current, receives the data signal, and outputs a compared data signal. The clock comparator, driven with a clock bias current, receives the clock signal, and outputs a compared clock signal. The flip-flop receives the compared data signal via the data intermediate circuit and the compared clock signal via the clock intermediate circuit. The phase difference between the compared data signal and the compared clock signal is improved by adjusting the data and the clock bias currents.
摘要翻译：提供接收电路，用于接收作为RSDS信号的数据信号和时钟信号，并将输出数据信号输出到数据驱动器。接收电路包括数据比较器，数据中间电路，时钟比较器，时钟中间和触发器。由数据偏置电流驱动的数据比较器接收数据信号，并输出比较的数据信号。由时钟偏置电流驱动的时钟比较器接收时钟信号，并输出比较的时钟信号。触发器经由时钟中间电路经由数据中间电路和经比较的时钟信号接收比较的数据信号。通过调整数据和时钟偏置电流，可以提高比较数据信号与比较时钟信号之间的相位差。

4. 发明授权

US06670939B2 Single-ended high-voltage level shifter for a TFT-LCD gate driver 有权
公开(公告)号：US06670939B2
公开(公告)日：2003-12-30
申请号：US09893213
申请日：2001-06-26
申请人： Tsen-Shau Yang , Chin-Chieh Chao , Chien-Kuo Wang
发明人： Tsen-Shau Yang , Chin-Chieh Chao , Chien-Kuo Wang
IPC分类号： G09G336
CPC分类号： G09G3/3677 , G09G2310/0289
摘要： A single-ended high-voltage level shifter for a TFT-LCD gate driver comprises a high-voltage power supply and a low-voltage power supply, a low-voltage NMOS transistor, a high-voltage NMOS transistor, and a high-voltage PMOS transistor. An input signal is applied at the gate of the low-voltage NMOS transistor. The source of the low-voltage NMOS transistor is connected to the low-voltage power supply. The source of the high-voltage NMOS transistor is connected to the drain of the low-voltage NMOS transistor. The high-voltage NMOS transistor has a first reference voltage applied at its gate. The level of the first reference voltage is between the input-signal level and the high-voltage power supply. The drain of the high-voltage PMOS transistor is connected to the drain of the high-voltage NMOS transistor. The source of the high-voltage PMOS transistor is connected to the high-voltage power supply. The high-voltage PMOS transistor has a second reference voltage applied at its gate. The second reference voltage keeps the high-voltage PMOS transistor in ON-state and is at a level higher than the first reference voltage. The drain of the high-voltage PMOS transistor is employed as the output end connected to an output buffer of the next stage.

5. 发明授权

US08786641B2 Digital-to-analog converter and method thereof 有权
标题翻译：数模转换器及其方法
公开(公告)号：US08786641B2
公开(公告)日：2014-07-22
申请号：US12078993
申请日：2008-04-09
申请人： Ko-Yang Tso , Hui-Wen Miao , Chin-Chieh Chao
发明人： Ko-Yang Tso , Hui-Wen Miao , Chin-Chieh Chao
IPC分类号： G09G5/10
CPC分类号： H03M1/765 , G09G3/3688 , G09G2310/027 , G09G2310/0289 , G09G2320/0276
摘要： A digital-to-analog (D/A) converter comprises a decoder apparatus and an operational amplifier. The decoder apparatus comprises first and second decoder unit. The first decoder unit selects a voltage of first voltage set as first and second voltage in response to a value of first gray level set. The second decoder unit selects first border voltage of second voltage set as the first and the second voltages and second border voltage of that as the first and the second voltages in response to the maximum and the minimum value of second gray level set respectively. The second decoder unit further selects the first and the second boarder voltage as the first and the second voltage respectively in response to an intermediate value of the second gray level set. The operational amplifier generates a pixel voltage having level between the first and the second voltage accordingly.
摘要翻译：数模（D / A）转换器包括解码器装置和运算放大器。解码器装置包括第一和第二解码器单元。第一解码器单元响应于设置的第一灰度级的值选择第一电压的电压作为第一和第二电压。第二解码器单元响应于分别设置的第二灰度级的最大值和最小值，选择作为第一和第二电压的第一电压和第二电压的第一电压和第二边界电压作为第一和第二电压。第二解码器单元还响应于第二灰度级的中间值，分别选择第一和第二边缘电压作为第一和第二电压。运算放大器相应地产生具有在第一和第二电压之间的电平的像素电压。

6. 发明授权

US08767899B2 Sampling phase selection method for a stream of data bits 有权
标题翻译：用于数据位流的采样相位选择方法
公开(公告)号：US08767899B2
公开(公告)日：2014-07-01
申请号：US13603097
申请日：2012-09-04
申请人： Ren-Feng Huang , Hui Wen Miao , Ko-Yang Tso , Chin-Chieh Chao
发明人： Ren-Feng Huang , Hui Wen Miao , Ko-Yang Tso , Chin-Chieh Chao
IPC分类号： H04L7/00
CPC分类号： H04L25/068
摘要： The current disclosure discloses a sampling phase selection method for a data stream, wherein the data stream has a variable data rate in a fixed time period. The method comprises the following steps: generating M section signals with the same time interval during the fixed time period of the data stream, generating N continuous clock phases according to a rising edge of each of the section signals, selecting one of the continuous clock phases corresponding to the different section signals in turn to provide a sampling phase, performing a plurality of samplings on the data stream to generate a flag signal, repeating the selecting and the sampling steps to generate N flag signals corresponding to the different section signals, and selecting a final sampling phase according to the N flag signals corresponding to the different section signals.
摘要翻译：本公开公开了一种用于数据流的采样相位选择方法，其中数据流在固定时间段内具有可变数据速率。该方法包括以下步骤：在数据流的固定时间段内产生具有相同时间间隔的M段信号，根据每个段信号的上升沿产生N个连续时钟相位，选择连续时钟相位对应于不同的部分信号又提供采样相位，在数据流上执行多个采样以产生标志信号，重复选择和采样步骤以产生对应于不同部分信号的N个标志信号，以及选择根据对应于不同部分信号的N个标志信号的最终采样相位。

7. 发明授权

US08594263B2 Sampling clock selection module of serial data stream 有权
标题翻译：串行数据流采样时钟选择模块
公开(公告)号：US08594263B2
公开(公告)日：2013-11-26
申请号：US13448677
申请日：2012-04-17
申请人： Ren-Feng Huang , Hui Wen Miao , Ko-Yang Tso , Chin-Chieh Chao
发明人： Ren-Feng Huang , Hui Wen Miao , Ko-Yang Tso , Chin-Chieh Chao
IPC分类号： H04L7/00
CPC分类号： G06F13/4291 , H04L7/0004 , H04L7/0337 , H04L7/046
摘要： A sampling clock selection module for a serial data stream is disclosed. The sampling clock selection module includes a multi-phase generation circuit, a sampling circuit, a comparison unit and a logic operation unit. The multi-phase generation circuit generates a plurality of non-overlapping clock phases derived from a reference clock signal. The phase selection circuit selects a sampling clock phase under a calibration mode. The sampling circuit performs sampling on the serial data stream a plurality of times to generate a plurality of sampled values in response to the sampling clock phase. The comparison unit compares the sampled values with the serial data stream so as to update a plurality of flag signals. The logic operation unit performs a logic operation on the flag signals so as to select a sampling clock phase under a normal operation mode from the clock phases.
摘要翻译：公开了一种用于串行数据流的采样时钟选择模块。采样时钟选择模块包括多相产生电路，采样电路，比较单元和逻辑运算单元。多相产生电路产生从参考时钟信号导出的多个非重叠时钟相位。相位选择电路在校准模式下选择采样时钟相位。采样电路对串行数据流进行多次采样，以响应采样时钟相位产生多个采样值。比较单元将采样值与串行数据流进行比较，以更新多个标志信号。逻辑运算部对标志信号进行逻辑运算，从时钟相位选择正常工作模式下的采样时钟相位。

8. 发明申请

US20130058445A1 SAMPLING PHASE SELECTION METHOD FOR A STREAM OF DATA BITS 有权
标题翻译：数据位流的采样相位选择方法
公开(公告)号：US20130058445A1
公开(公告)日：2013-03-07
申请号：US13603097
申请日：2012-09-04
申请人： REN-FENG HUANG , HUI WEN MIAO , KO-YANG TSO , CHIN-CHIEH CHAO
发明人： REN-FENG HUANG , HUI WEN MIAO , KO-YANG TSO , CHIN-CHIEH CHAO
IPC分类号： H04L7/00
CPC分类号： H04L25/068
摘要： The current disclosure discloses a sampling phase selection method for a data stream, wherein the data stream has a variable data rate in a fixed time period. The method comprises the following steps: generating M section signals with the same time interval during the fixed time period of the data stream, generating N continuous clock phases according to a rising edge of each of the section signals, selecting one of the continuous clock phases corresponding to the different section signals in turn to provide a sampling phase, performing a plurality of samplings on the data stream to generate a flag signal, repeating the selecting and the sampling steps to generate N flag signals corresponding to the different section signals, and selecting a final sampling phase according to the N flag signals corresponding to the different section signals.
摘要翻译：本公开公开了一种用于数据流的采样相位选择方法，其中数据流在固定时间段内具有可变数据速率。该方法包括以下步骤：在数据流的固定时间段内产生具有相同时间间隔的M段信号，根据每个段信号的上升沿产生N个连续时钟相位，选择连续时钟相位对应于不同的部分信号又提供采样相位，在数据流上执行多个采样以产生标志信号，重复选择和采样步骤以产生对应于不同部分信号的N个标志信号，以及选择根据对应于不同部分信号的N个标志信号的最终采样相位。

9. 发明申请

US20120075263A1 DRIVING CIRCUIT AND OPERATING METHOD THEREOF 审中-公开
标题翻译：驱动电路及其工作方法
公开(公告)号：US20120075263A1
公开(公告)日：2012-03-29
申请号：US13215770
申请日：2011-08-23
申请人： Ko-Yang Tso , Chi-Yuan Lu , Chin-Chieh Chao , Yu-Lung Lo
发明人： Ko-Yang Tso , Chi-Yuan Lu , Chin-Chieh Chao , Yu-Lung Lo
IPC分类号： G06F3/038
CPC分类号： G09G3/3685 , G09G3/3614 , G09G2300/0828 , G09G2300/0833 , G09G2310/0297
摘要： A driving circuit and an operating method thereof are disclosed. The driving circuit includes at least one first channel, at least one second channel, a selecting module, and at least one switching module. The selecting module is coupled to input ends of the first channel and the second channel. The at least one switching module is coupled to output ends of the at least one first channel and the at least one second channel. The selecting module and the switching module will perform corresponding switching actions to make the driving circuit selectively under a first operating mode or a second operating mode.
摘要翻译：公开了一种驱动电路及其操作方法。驱动电路包括至少一个第一通道，至少一个第二通道，选择模块和至少一个开关模块。选择模块耦合到第一通道和第二通道的输入端。所述至少一个开关模块耦合到所述至少一个第一通道和所述至少一个第二通道的输出端。选择模块和切换模块将执行相应的切换动作，以使驱动电路选择性地处于第一操作模式或第二操作模式。

10. 发明授权

US08004512B2 Power-on screen pattern correcting apparatus and source driver using the same 有权
标题翻译：上电屏幕图案校正装置和使用其的源驱动器
公开(公告)号：US08004512B2
公开(公告)日：2011-08-23
申请号：US12010354
申请日：2008-01-24
申请人： Yong-Nien Rao , Ko-Yang Tso , Hui-Wen Miao , Chin-Chieh Chao
发明人： Yong-Nien Rao , Ko-Yang Tso , Hui-Wen Miao , Chin-Chieh Chao
IPC分类号： G06F3/038
CPC分类号： G09G3/20 , G09G3/3275 , G09G3/3688 , G09G2310/0245 , G09G2310/0275 , G09G2320/0233
摘要： A power-on screen pattern correcting apparatus is for correcting start output data of output terminals of a source driver such that a power-on screen pattern of a display is substantially uniform. The correcting apparatus comprises a flip-flop, a first logic unit and a second logic unit. The flip-flop controls a level of an inner signal to be substantially equal to a low signal level in response to a low level of a power start signal. The first logic unit enables a first signal in response to the low level of the inner signal or a low level of a high-impedance control signal. The second logic unit enables a second signal such that the output terminals are coupled to a charge sharing line and the power-on screen pattern is uniform in response to the low level of the inner signal or a low level of a charge-sharing control signal.
摘要翻译：上电屏幕图案校正装置用于校正源驱动器的输出端的开始输出数据，使得显示器的开机屏幕图案基本上均匀。校正装置包括触发器，第一逻辑单元和第二逻辑单元。触发器响应于低电平的功率启动信号而控制内部信号的电平基本上等于低信号电平。第一逻辑单元响应于内部信号的低电平或高电平的高阻抗控制信号而启用第一信号。第二逻辑单元启用第二信号，使得输出端耦合到电荷共享线，并且电源屏幕图案响应于内部信号的低电平或电荷共享控制信号的低电平而均匀。

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