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    • 1. 发明授权
    • Rail-to-rail comparator
    • 轨到轨比较器
    • US08638126B2
    • 2014-01-28
    • US13352963
    • 2012-01-18
    • Chieh-Min LoTzu-Huan ChiuChien-Sheng ChenChien-Ping Lu
    • Chieh-Min LoTzu-Huan ChiuChien-Sheng ChenChien-Ping Lu
    • H03K5/22
    • H03F3/45219H03K5/2481
    • The present invention discloses a rail-to-rail comparator. The rail-to-rail comparator includes: a positive voltage rail providing a positive supply voltage, a ground voltage rail providing a ground voltage, an input stage, and an output stage. The input stage includes: a positive and a negative input terminals for receiving a first input signal and a second input signal; a first differential amplifier circuit, which includes a pair of depletion NMOS transistors to generate a first pair of differential currents; and a second differential amplifier circuit, which includes a pair of native NMOS transistors to generate a second pair of differential currents. The output stage is coupled to the first differential amplifier circuit and the second differential amplifier circuit, and generates an output signal related to a difference between the first input signal and the second input signal.
    • 本发明公开了一种轨对轨比较器。 轨到轨比较器包括:提供正电源电压的正电压轨,提供接地电压的接地电压轨,输入级和输出级。 输入级包括:用于接收第一输入信号和第二输入信号的正和负输入端; 第一差分放大器电路,其包括一对耗尽NMOS晶体管,以产生第一对差分电流; 以及第二差分放大器电路,其包括一对天线NMOS晶体管以产生第二对差分电流。 输出级耦合到第一差分放大器电路和第二差分放大器电路,并且产生与第一输入信号和第二输入信号之间的差有关的输出信号。
    • 5. 发明申请
    • Platform-Based Idle-Time Processing
    • 基于平台的空闲时间处理
    • US20100031071A1
    • 2010-02-04
    • US12182074
    • 2008-07-29
    • Chien-Ping LUStephen D. LewRobert William Chapman
    • Chien-Ping LUStephen D. LewRobert William Chapman
    • G06F1/32
    • G06F1/3203
    • A system and method for transitions a computing system between operating modes that have different power consumption characteristics. When a system management unit (SMU) determines that the computing system is in a low activity state, the SMU transitions the central processing unit (CPU) into a low power operating mode after the CPU stores critical operating state of the CPU in a memory. The SMU then intercepts and processes interrupts intended for the CPU, modifying a copy of the critical operating state. This effectively extends the time during which the CPU stays in lower power mode. When the SMU determines that the computing system exits a low activity state, the copy of the critical operating state is stored in the memory and the SMU transitions the CPU into a high power operating mode using the modified critical operating state.
    • 一种用于在具有不同功耗特性的操作模式之间转换计算系统的系统和方法。 当系统管理单元(SMU)确定计算系统处于低活动状态时,在CPU将CPU的临界操作状态存储在存储器中之后,SMU将中央处理单元(CPU)转换为低功耗操作模式。 然后,SMU拦截并处理用于CPU的中断,修改关键操作状态的副本。 这有效地延长了CPU处于较低功耗模式的时间。 当SMU确定计算系统退出低活动状态时,关键操作状态的副本存储在存储器中,并且SMU使用修改的关键操作状态将CPU转换为高功率​​操作模式。
    • 6. 发明授权
    • Charging control circuit
    • 充电控制电路
    • US08917062B2
    • 2014-12-23
    • US13597653
    • 2012-08-29
    • Chien-Ping LuNien-Hui KungLi-Wei LeeChia-Hsiang LinChen-Hsiang HsiaoKo-Ching Su
    • Chien-Ping LuNien-Hui KungLi-Wei LeeChia-Hsiang LinChen-Hsiang HsiaoKo-Ching Su
    • H02J7/00H02J7/16H02J7/06
    • H02J7/0072
    • The present invention discloses a charge control circuit for supplying power from an external power source to a first common node and charging a second common node from the first common node. A regulator circuit is coupled between the external power source and the first common node, and a transistor is coupled between the first common node and the second common node. The present invention detects an operation parameter of the transistor and controls an internal voltage source to generate a non-predetermined voltage difference accordingly. When the sum of the voltage at the second common node and the non-predetermined voltage is equal to or higher than the reference voltage, the voltage at the first common node is regulated to a level higher than the voltage at the second common node, and the transistor is in an optimum conductive state.
    • 本发明公开了一种用于从外部电源向第一公共节点提供电力并从第一公共节点对第二公共节点充电的充电控制电路。 调节器电路耦合在外部电源和第一公共节点之间,并且晶体管耦合在第一公共节点和第二公共节点之间。 本发明检测晶体管的操作参数,并且控制内部电压源以相应地产生非预定的电压差。 当第二公共节点和非预定电压之间的电压之和等于或高于参考电压时,第一公共节点处的电压被调节到高于第二公共节点处的电压的电平,以及 晶体管处于最佳导通状态。
    • 7. 发明申请
    • RAIL-TO-RAIL COMPARATOR
    • 轨至轨比较器
    • US20130181776A1
    • 2013-07-18
    • US13352963
    • 2012-01-18
    • CHIEH-MIN LOTzu-Huan ChiuChien-Sheng ChenChien-Ping Lu
    • CHIEH-MIN LOTzu-Huan ChiuChien-Sheng ChenChien-Ping Lu
    • H03F3/45
    • H03F3/45219H03K5/2481
    • The present invention discloses a rail-to-rail comparator. The rail-to-rail comparator includes: a positive voltage rail providing a positive supply voltage, a ground voltage rail providing a ground voltage, an input stage, and an output stage. The input stage includes: a positive and a negative input terminals for receiving a first input signal and a second input signal; a first differential amplifier circuit, which includes a pair of depletion NMOS transistors to generate a first pair of differential currents; and a second differential amplifier circuit, which includes a pair of native NMOS transistors to generate a second pair of differential currents. The output stage is coupled to the first differential amplifier circuit and the second differential amplifier circuit, and generates an output signal related to a difference between the first input signal and the second input signal.
    • 本发明公开了一种轨对轨比较器。 轨到轨比较器包括:提供正电源电压的正电压轨,提供接地电压的接地电压轨,输入级和输出级。 输入级包括:用于接收第一输入信号和第二输入信号的正和负输入端; 第一差分放大器电路,其包括一对耗尽NMOS晶体管,以产生第一对差分电流; 以及第二差分放大器电路,其包括一对天线NMOS晶体管以产生第二对差分电流。 输出级耦合到第一差分放大器电路和第二差分放大器电路,并且产生与第一输入信号和第二输入信号之间的差有关的输出信号。
    • 8. 发明授权
    • Boost driver circuit with fast discharging function
    • 升压驱动电路具有快速放电功能
    • US07994728B2
    • 2011-08-09
    • US12384154
    • 2009-04-01
    • Kwan-Jen ChuNien-Hui KungTzu-Huan ChiuChien-Ping Lu
    • Kwan-Jen ChuNien-Hui KungTzu-Huan ChiuChien-Ping Lu
    • H05B37/00
    • H05B33/0815Y02B20/346
    • The present invention discloses a boost driver circuit which converts an input voltage to an output voltage and supplies it to a load, the boost driver circuit comprising: a power transistor electrically connected with a node between the input voltage and the output voltage; a pulse width modulation driver circuit for controlling the operation of the power transistor; an output node electrically connected with the output voltage; a feedback node electrically connected with the load; a low voltage transistor electrically connected with the feedback node; and a clamp and fast discharge circuit electrically connected with the feedback node for discharging the feedback node when the voltage at the feedback node is higher than a predetermined voltage.
    • 本发明公开了一种升压驱动器电路,其将输入电压转换为输出电压并将其提供给负载,该升压驱动电路包括:功率晶体管,其与输入电压和输出电压之间的节点电连接; 用于控制功率晶体管的操作的脉宽调制驱动电路; 与输出电压电连接的输出节点; 与负载电连接的反馈节点; 与所述反馈节点电连接的低压晶体管; 以及与反馈节点电连接的用于在反馈节点处的电压高于预定电压时对反馈节点放电的钳位和快速放电电路。