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1. 发明申请

US20110298026A1 LOGIC-BASED eDRAM USING LOCAL INTERCONNECTS TO REDUCE IMPACT OF EXTENSION CONTACT PARASITICS 有权
标题翻译：基于逻辑的eDRAM使用本地互连来减少扩展联系人的影响
公开(公告)号：US20110298026A1
公开(公告)日：2011-12-08
申请号：US13046973
申请日：2011-03-14
申请人： John G. Jansen , Chi-Yi Kao , Ce Chen , Shahriar Moinian
发明人： John G. Jansen , Chi-Yi Kao , Ce Chen , Shahriar Moinian
IPC分类号： H01L27/108 , H01L21/28
CPC分类号： H01L27/10894 , H01L27/10855 , H01L27/10882 , H01L27/10888 , H01L27/10897
摘要： An electronic device includes an active layer located over a substrate with the active layer having a logic circuit and an eDRAM cell. The electronic device also includes a first metallization level located over the active layer that provides logic interconnects and metal capacitor plates. The logic interconnects are connected to the logic circuit and the metal capacitor plates are connected to the eDRAM cell. The electronic device additionally includes a second metallization level located over the first metallization level that provides an interconnect connected to at least one of the logic interconnects, and a bit line that is connected to the eDRAM cell. A method of manufacturing an electronic device is also included.
摘要翻译：电子器件包括位于衬底上方的有源层，有源层具有逻辑电路和eDRAM单元。电子器件还包括位于有源层上的第一金属化级，其提供逻辑互连和金属电容器板。逻辑互连连接到逻辑电路，金属电容器板连接到eDRAM单元。电子设备还包括位于第一金属化级别上的第二金属化级别，其提供连接到至少一个逻辑互连的互连线以及连接到eDRAM单元的位线。还包括制造电子装置的方法。

2. 发明申请

US20100105357A1 APPARATUS AND METHOD FOR RENEWING A KEY, COMPUTER READABLE MEDIUM THEREOF AND WIRELESS NETWORK COMPRISING THE SAME 审中-公开
标题翻译：一种重要的计算机可读介质及包含其的无线网络的装置和方法
公开(公告)号：US20100105357A1
公开(公告)日：2010-04-29
申请号：US12337015
申请日：2008-12-17
申请人： FRANK CHEE-DA TSAI , CHIEN-CHIEN CHIU , I-HUNG LIN , HUNG-MIN SUN , SHIH-YING CHANG , CHIEH HSING , CHI-YI KAO
发明人： FRANK CHEE-DA TSAI , CHIEN-CHIEN CHIU , I-HUNG LIN , HUNG-MIN SUN , SHIH-YING CHANG , CHIEH HSING , CHI-YI KAO
IPC分类号： H04W12/04
CPC分类号： H04L63/06 , H04L9/0872 , H04L9/0891 , H04L2209/80 , H04W12/00502 , H04W12/04 , H04W36/0038
摘要： An apparatus and method for renewing a key, a computer readable media thereof, and a wireless network comprising the same are provided. The method is adapted to the first base station. The first base station belongs to a wireless network. The first base station uses a first key and has a first coverage. The method comprises the following steps: determining that the mobile device moves from the first coverage to the second coverage of a second base station; determining that the login time of the mobile device is later than the renewing time of the first key; renewing the first key; and sending the first key to the mobile device.
摘要翻译：提供了一种用于更新密钥的装置和方法，其计算机可读介质和包括其的无线网络。该方法适用于第一基站。第一个基站属于无线网络。第一个基站使用第一个密钥并具有第一个密钥。该方法包括以下步骤：确定移动设备从第一覆盖移动到第二基站的第二覆盖; 确定所述移动设备的登录时间晚于所述第一密钥的更新时间; 更新第一个关键; 以及将所述第一密钥发送到所述移动设备。

3. 发明申请

US20090304076A1 MEMORY ARRANGEMENT METHOD AND SYSTEM FOR AC/DC PREDICTION IN VIDEO COMPRESSION APPLICATIONS BASED ON PARALLEL PROCESSING 审中-公开
标题翻译：基于平行处理的视频压缩应用中AC / DC预测的存储器布置方法和系统
公开(公告)号：US20090304076A1
公开(公告)日：2009-12-10
申请号：US12347496
申请日：2008-12-31
申请人： Po-Chun Chung , Guo-Zua Wu , Wei-Zheng Lu , Nai-Shen Wu , Chi-Yi Kao , Hsin-Han Shen
发明人： Po-Chun Chung , Guo-Zua Wu , Wei-Zheng Lu , Nai-Shen Wu , Chi-Yi Kao , Hsin-Han Shen
IPC分类号： H04N7/32
CPC分类号： H04N19/436 , H04N19/423 , H04N19/593
摘要： A memory arrangement method and system for AC/DC prediction in video compression applications based on parallel processing is disclosed. The method and system achieves optimum operating efficiency for data operation and reading based on parallel computing characteristics (Single Instruction Multiple Data (SIMD)) of an operation unit of the system. Additionally, the method transplants a VC-1 video compression system running in an operating system (the Windows operating system, for example) to a system platform using a digital signal processor (DSP) as an operation unit and implements a real-time VC-1 encoder according to parallel computing characteristics of a hardware core of the system platform.
摘要翻译：公开了一种用于基于并行处理的视频压缩应用中的AC / DC预测的存储器布置方法和系统。该方法和系统基于系统操作单元的并行计算特性（单指令多数据（SIMD））实现数据操作和读取的最佳操作效率。此外，该方法将在操作系统（例如Windows操作系统）中运行的VC-1视频压缩系统移植到使用数字信号处理器（DSP）作为操作单元的系统平台，并且实现实时VC- 1编码器根据系统平台的硬件核心的并行计算特性。

4. 发明授权

US5719084A Method for the controlled formation of voids in doped glass dielectric films 失效
标题翻译：在掺杂的玻璃介电膜中控制形成空隙的方法
公开(公告)号：US5719084A
公开(公告)日：1998-02-17
申请号：US564922
申请日：1995-11-29
申请人： Thomas G. Mallon , Chi-yi Kao , Wei-jen Hsia , Atsushi Shimoda
发明人： Thomas G. Mallon , Chi-yi Kao , Wei-jen Hsia , Atsushi Shimoda
IPC分类号： H01L21/31 , H01L21/3105 , H01L21/316 , H01L21/768 , H01L21/469
CPC分类号： H01L21/31051 , H01L21/76819 , H01L21/7682
摘要： A method is provided for the controlled formation of voids in integrated circuit doped glass dielectric films. The film can be formed of borophosphosilica glass (BPSG) or other types of doped glass. The method involves the steps of providing a substrate on which conductors are formed, depositing a first layer of doped glass to a thickness in a predetermined ratio to the size of the space between conductors, reflowing the first doped glass layer, applying one or more additional doped glass layers to make up for any shortfall in desired total doped glass thickness, and performing a high temperature densification to smooth each additional layer. The method provides for increased integrated circuit speed by controlled formation of voids which have a low dielectric constant and therefore reduce capacitance between adjacent conductors. The method can be performed using existing doped glass deposition and reflow equipment.
摘要翻译：提供了一种用于在集成电路掺杂的玻璃介电膜中控制形成空隙的方法。该膜可由硼磷石玻璃（BPSG）或其他类型的掺杂玻璃形成。该方法包括以下步骤：提供其上形成有导体的基板，将第一掺杂玻璃层以与导体之间的空间的尺寸预定比例的厚度沉积，回流第一掺杂玻璃层，施加一个或多个附加掺杂的玻璃层以弥补所需的总掺杂玻璃厚度的任何不足，并且执行高温致密化以平滑每个附加层。该方法通过控制形成具有低介电常数并因此降低相邻导体之间的电容的空隙来提供增加的集成电路速度。该方法可以使用现有的掺杂玻璃沉积和回流设备进行。

5. 发明授权

US5717238A Substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant forming P-LDD region of a PMOS device 失效
标题翻译：具有受控量的惰性气体离子的衬底，以减少形成PMOS器件的P-LDD区域的硼掺杂物的沟道和/或扩散
公开(公告)号：US5717238A
公开(公告)日：1998-02-10
申请号：US677078
申请日：1996-07-09
申请人： Sheldon Aronowitz , James Kimball , Yu-Lam Ho , Gobi Padmanabhan , Douglas T. Grider , Chi-Yi Kao
发明人： Sheldon Aronowitz , James Kimball , Yu-Lam Ho , Gobi Padmanabhan , Douglas T. Grider , Chi-Yi Kao
IPC分类号： H01L21/265 , H01L21/336 , H01L29/76 , H01L29/94
CPC分类号： H01L29/6659 , H01L21/26506
摘要： A process and resulting product are described for controlling the channeling and/or diffusion of a boron dopant in a P- region forming the lightly doped drain (LDD) region of a PMOS device in a single crystal semiconductor substrate, such as a silicon substrate. The channeling and/or diffusion of the boron dopant is controlled by implanting the region, prior to implantation with a boron dopant, with noble gas ions, such as argon ions, at a dosage at least equal to the subsequent dosage of the implanted boron dopant, but not exceeding an amount equivalent to the implantation of about 3.times.10.sup.14 argon ions/cm.sup.2 into a silicon substrate, whereby channeling and diffusion of the subsequently implanted boron dopant is inhibited without, however, amorphizing the semiconductor substrate.
摘要翻译：描述了一种工艺和产生的产品，用于控制在诸如硅衬底的单晶半导体衬底中形成PMOS器件的轻掺杂漏极（LDD）区域的P区中的硼掺杂剂的沟道化和/或扩散。硼掺杂剂的通道和/或扩散通过在用硼掺杂剂注入之前用惰性气体离子（例如氩离子）注入该区域，剂量至少等于注入的硼掺杂剂的后续剂量但不超过等于将约3×1014个氩离子/ cm 2注入到硅衬底中的量的量，由此抑制随后注入的硼掺杂剂的引导和扩散，而不会使半导体衬底非晶化。

6. 发明授权

US5585286A Implantation of a semiconductor substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant subsequently implanted into the substrate to form P- LDD region of a PMOS device 失效
标题翻译：将具有受控量的惰性气体离子的半导体衬底植入以减少随后注入到衬底中的硼掺杂物的沟道和/或扩散以形成PMOS器件的P-LDD区
公开(公告)号：US5585286A
公开(公告)日：1996-12-17
申请号：US521795
申请日：1995-08-31
申请人： Sheldon Aronowitz , James Kimball , Yu-Lam Ho , Gobi Padmanabhan , Douglas T. Grider , Chi-Yi Kao
发明人： Sheldon Aronowitz , James Kimball , Yu-Lam Ho , Gobi Padmanabhan , Douglas T. Grider , Chi-Yi Kao
IPC分类号： H01L21/265 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/26506
摘要： A process and resulting product are described for controlling the channeling and/or diffusion of a boron dopant in a P- region forming the lightly doped drain (LDD) region of a PMOS device in a single crystal semiconductor substrate, such as a silicon substrate. The channeling and/or diffusion of the boron dopant is controlled by implanting the region, prior to implantation with a boron dopant,, with noble gas ions, such as argon ions, at a dosage at least equal to the subsequent dosage of the implanted boron dopant, but not exceeding an amount equivalent to the implantation of about 3.times.10.sup.13 argon ions/cm.sup.2 into a silicon substrate, whereby channeling and diffusion of the subsequently implanted boron dopant is inhibited without, however, amorphizing the semiconductor substrate.
摘要翻译：描述了一种工艺和产生的产品，用于控制在诸如硅衬底的单晶半导体衬底中形成PMOS器件的轻掺杂漏极（LDD）区域的P区中的硼掺杂剂的沟道化和/或扩散。硼掺杂剂的通道和/或扩散通过在用硼掺杂剂注入之前用惰性气体离子（例如氩离子）注入该区域，剂量至少等于注入硼的后续剂量掺杂剂，但不超过与硅衬底中注入约3×1013氩离子/ cm 2相当的量，由此抑制随后注入的硼掺杂剂的通道化和扩散，而不会使半导体衬底非晶化。

7. 发明授权

US5278103A Method for the controlled formation of voids in doped glass dielectric films 失效
标题翻译：在掺杂的玻璃介电膜中控制形成空隙的方法
公开(公告)号：US5278103A
公开(公告)日：1994-01-11
申请号：US23304
申请日：1993-02-26
申请人： Thomas G. Mallon , Chi-yi Kao , Wei-jen Hsia , Atsushi Shimoda
发明人： Thomas G. Mallon , Chi-yi Kao , Wei-jen Hsia , Atsushi Shimoda
IPC分类号： H01L21/31 , H01L21/3105 , H01L21/316 , H01L21/768 , H01L21/473
CPC分类号： H01L21/31051 , H01L21/76819 , H01L21/7682
摘要： A method is provided for the controlled formation of voids in integrated circuit doped glass dielectric films. The film can be formed of borophosphosilica glass (BPSG) or other types of doped glass. The method involves the steps of providing a substrate on which conductors are formed, depositing a first layer of doped glass to a thickness in a predetermined ratio to the size of the space between conductors, reflowing the first doped glass layer, applying one or more additional doped glass layers to make up for any shortfall in desired total doped glass thickness, and performing a high temperature densification to smooth each additional layer. The method provides for increased integrated circuit speed by controlled formation of voids which have a low dielectric constant and therefore reduce capacitance between adjacent conductors. The method can be performed using existing doped glass deposition and reflow equipment.
摘要翻译：提供了一种用于在集成电路掺杂的玻璃介电膜中控制形成空隙的方法。该膜可由硼磷石玻璃（BPSG）或其他类型的掺杂玻璃形成。该方法包括以下步骤：提供其上形成有导体的基板，将第一掺杂玻璃层以与导体之间的空间的尺寸预定比例的厚度沉积，回流第一掺杂玻璃层，施加一个或多个附加掺杂的玻璃层以弥补所需的总掺杂玻璃厚度的任何不足，并且执行高温致密化以平滑每个附加层。该方法通过控制形成具有低介电常数并因此降低相邻导体之间的电容的空隙来提供增加的集成电路速度。该方法可以使用现有的掺杂玻璃沉积和回流设备进行。

8. 发明授权

US08283713B2 Logic-based eDRAM using local interconnects to reduce impact of extension contact parasitics 有权
标题翻译：基于逻辑的eDRAM使用局部互连来减少延长触点寄生效应的影响
公开(公告)号：US08283713B2
公开(公告)日：2012-10-09
申请号：US13046973
申请日：2011-03-14
申请人： John G. Jansen , Chi-Yi Kao , Ce Chen , Shahriar Moinian
发明人： John G. Jansen , Chi-Yi Kao , Ce Chen , Shahriar Moinian
IPC分类号： H01L27/108
CPC分类号： H01L27/10894 , H01L27/10855 , H01L27/10882 , H01L27/10888 , H01L27/10897
摘要： An electronic device includes an active layer located over a substrate with the active layer having a logic circuit and an eDRAM cell. The electronic device also includes a first metallization level located over the active layer that provides logic interconnects and metal capacitor plates. The logic interconnects are connected to the logic circuit and the metal capacitor plates are connected to the eDRAM cell. The electronic device additionally includes a second metallization level located over the first metallization level that provides an interconnect connected to at least one of the logic interconnects, and a bit line that is connected to the eDRAM cell. A method of manufacturing an electronic device is also included.
摘要翻译：电子器件包括位于衬底上方的有源层，有源层具有逻辑电路和eDRAM单元。电子器件还包括位于有源层上的第一金属化级，其提供逻辑互连和金属电容器板。逻辑互连连接到逻辑电路，金属电容器板连接到eDRAM单元。电子设备还包括位于第一金属化级别上的第二金属化级别，其提供连接到至少一个逻辑互连的互连线以及连接到eDRAM单元的位线。还包括制造电子装置的方法。

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