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1. 发明申请

US20090187874A1 CIRCUIT AND CIRCUIT DESIGN METHOD 审中-公开
标题翻译：电路与电路设计方法
公开(公告)号：US20090187874A1
公开(公告)日：2009-07-23
申请号：US12015627
申请日：2008-01-17
申请人： Mao-Lin Wu , Shih-Hung Lin , Hua Wu , Che Yuan Jao , Ching-Chih Li , Sheng-Ming Chang
发明人： Mao-Lin Wu , Shih-Hung Lin , Hua Wu , Che Yuan Jao , Ching-Chih Li , Sheng-Ming Chang
IPC分类号： G06F17/50
CPC分类号： H05K1/0216 , H01R12/79 , H05K1/0237 , H05K2201/09236 , H05K2201/10166 , H05K2201/10689
摘要： A circuit and a circuit design method are provided. The circuit operates between a first power source voltage and a ground voltage. The circuit comprises at least one low speed circuit path and at least one high speed circuit path. The low speed circuit path adjusts voltage level at the first power source voltage or the ground voltage. The low speed circuit path provides a first return path and isolates unwanted noise signals for a signal on the high speed circuit path.
摘要翻译：提供电路和电路设计方法。该电路在第一电源电压和接地电压之间工作。该电路包括至少一个低速电路路径和至少一个高速电路路径。低速电路路径调整第一电源电压或接地电压时的电压电平。低速电路路径提供第一返回路径并隔离高速电路路径上的信号的不需要的噪声信号。

2. 发明授权

US08692605B2 Receiving circuits for core circuits 有权
标题翻译：核心电路接收电路
公开(公告)号：US08692605B2
公开(公告)日：2014-04-08
申请号：US13169467
申请日：2011-06-27
申请人： Che-Yuan Jao
发明人： Che-Yuan Jao
IPC分类号： H03K5/08 , H03K19/00
CPC分类号： H03K19/00 , H03K5/08 , H03K5/2472
摘要： A receiving circuit for a core circuit is provided and includes a first receiving-path unit. The first receiving-path unit is capable of receiving an input signal and outputting an output signal to the core circuit according to the input signal. The first receiving-path unit includes an input buffer which is capable of operating in a core power domain of the core circuit and receiving a first clamped signal. When a level of the input signal is substantially equal to or lower than a first predetermined voltage level, the input signal is passed to the input buffer to serve as the first clamped signal, and the input buffer is capable of outputting the output signal in the core power domain according to the first clamped signal. When the level of the input signal is higher than the first predetermined voltage level, the input signal is not passed to the input buffer.
摘要翻译：提供了一种用于核心电路的接收电路，并且包括第一接收路径单元。第一接收路径单元能够接收输入信号，并根据输入信号向核心电路输出输出信号。第一接收路径单元包括能够在核心电路的核心电源域中操作并接收第一钳位信号的输入缓冲器。当输入信号的电平基本上等于或低于第一预定电压电平时，输入信号被传递到输入缓冲器以用作第一钳位信号，并且输入缓冲器能够输出输出信号核心电源域根据第一个钳位信号。当输入信号的电平高于第一预定电压电平时，输入信号不会传递到输入缓冲器。

3. 发明授权

US08258615B2 Semiconductor device and fabricating method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08258615B2
公开(公告)日：2012-09-04
申请号：US12389388
申请日：2009-02-20
申请人： Sheng-Ming Chang , Che-Yuan Jao , Ching-Chih Li
发明人： Sheng-Ming Chang , Che-Yuan Jao , Ching-Chih Li
IPC分类号： H01L23/498
CPC分类号： H01L23/642 , H01L23/3114 , H01L23/367 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/33 , H01L24/48 , H01L25/0657 , H01L2224/48091 , H01L2224/73215 , H01L2924/00014 , H01L2924/01033 , H01L2924/01077 , H01L2924/01082 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/3011 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention provides a semiconductor device capable of eliminating voltage (IR) drop of a semiconductor die inside the semiconductor device and a fabricating method of the semiconductor device. The semiconductor device comprises the semiconductor die, and the semiconductor die comprises a first surface area, a plurality of first pads potentially equivalent to each other, a passivation layer, a plurality of first openings, and a first conducting medium layer. The passivation layer is disposed on the plurality of first pads. The plurality of first openings is formed on the passivation layer, and utilized for exposing the plurality of first pads. The first conducting medium layer is formed on the first surface area, and utilized for fulfilling the plurality of first openings to connect the plurality of first pads.
摘要翻译：本发明提供能够消除半导体器件内的半导体管芯的电压（IR）下降的半导体器件以及半导体器件的制造方法。半导体器件包括半导体管芯，并且半导体管芯包括第一表面区域，潜在地相当于彼此的多个第一焊盘，钝化层，多个第一开口和第一导电介质层。钝化层设置在多个第一焊盘上。多个第一开口形成在钝化层上，并用于暴露多个第一焊盘。第一导电介质层形成在第一表面区域上，用于实现多个第一开口以连接多个第一焊盘。

4. 发明申请

US20100171211A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100171211A1
公开(公告)日：2010-07-08
申请号：US12350208
申请日：2009-01-07
申请人： Che-Yuan Jao , Sheng-Ming Chang
发明人： Che-Yuan Jao , Sheng-Ming Chang
IPC分类号： H01L23/488
CPC分类号： H01L24/06 , H01L23/50 , H01L23/552 , H01L24/05 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L25/0657 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/05599 , H01L2224/32145 , H01L2224/48091 , H01L2224/4813 , H01L2224/48137 , H01L2224/48139 , H01L2224/48145 , H01L2224/48147 , H01L2224/48463 , H01L2224/4847 , H01L2224/4911 , H01L2224/49111 , H01L2224/85399 , H01L2225/06506 , H01L2225/06527 , H01L2924/00014 , H01L2924/01014 , H01L2924/01027 , H01L2924/01033 , H01L2924/01076 , H01L2924/01077 , H01L2924/01082 , H01L2924/3025 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device is provided by the present invention. The semiconductor device includes a semiconductor die, and the semiconductor die includes a die core having at least two bond pads with voltage level equivalent to each other and electrically connected to each other via at least a bond wire, and an input/output (I/O) periphery. The semiconductor device of the present invention is capable of solving the IR drop of the semiconductor die with low cost.
摘要翻译：本发明提供一种半导体器件。所述半导体器件包括半导体管芯，并且所述半导体管芯包括具有至少两个接合焊盘的芯片，所述至少两个接合焊盘的电压水平彼此相等并且至少通过接合线彼此电连接，以及输入/输出（I / O）周边。本发明的半导体器件能够以低成本解决半导体管芯的IR下降。

5. 发明申请

US20080068910A1 MEMORY CIRCUITS PREVENTING FALSE PROGRAMMING 有权
标题翻译：存储器电路防止伪编程
公开(公告)号：US20080068910A1
公开(公告)日：2008-03-20
申请号：US11869196
申请日：2007-10-09
申请人： Che Yuan Jao
发明人： Che Yuan Jao
IPC分类号： G11C7/02
CPC分类号： G11C7/02 , G11C7/20 , G11C16/22 , G11C17/16 , G11C17/18
摘要： Memory circuits capable of preventing false programming caused by power-up sequence are provided, in which a programmable unit comprises a plurality of programmable elements, a source bus coupled between an external programming voltage and the programmable elements, a switching unit connected between the external programming voltage and the source bus, comprising a control terminal, and a level shifter, shifting a voltage level of an enabling signal to a first power voltage from a second power voltage lower than the external programming voltage. When the second power voltage is not ready during power up, the level shifter sets the control terminal of the switching unit to a predetermined logic level such that the switching unit is turned off and the source bus is disconnected from the external programming voltage thereby preventing false programming.
摘要翻译：提供了能够防止由上电序列引起的伪编程的存储器电路，其中可编程单元包括多个可编程元件，耦合在外部编程电压和可编程元件之间的源极总线，连接在外部编程电压和源极总线，包括控制端子和电平移位器，使能信号的电压电平从低于外部编程电压的第二电源电压移位到第一电源电压。当上电期间第二电源电压未准备好时，电平移位器将开关单元的控制端子设置为预定的逻辑电平，使得开关单元断开，并且源总线与外部编程电压断开，从而防止错误编程。

6. 发明授权

US08525310B2 Leadframe package for high-speed data rate applications 有权
标题翻译：用于高速数据速率应用的引线框封装
公开(公告)号：US08525310B2
公开(公告)日：2013-09-03
申请号：US13085446
申请日：2011-04-12
申请人： Nan-Jang Chen , Chun-Wei Chang , Sheng-Ming Chang , Che-Yuan Jao , Ching-Chih Li , Nan-Cheng Chen
发明人： Nan-Jang Chen , Chun-Wei Chang , Sheng-Ming Chang , Che-Yuan Jao , Ching-Chih Li , Nan-Cheng Chen
IPC分类号： H01L23/495
CPC分类号： H01L24/49 , H01L23/49503 , H01L23/49541 , H01L23/49551 , H01L24/48 , H01L2224/05554 , H01L2224/48177 , H01L2224/48247 , H01L2224/49109 , H01L2224/49175 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads disposed along peripheral edges of the die pad; a ground bar between the leads and the die pad; and a plurality of bridges connecting the ground bar with the die pad, wherein a gap between two adjacent bridges has a length that is equal to or less than 3 mm.
摘要翻译：半导体封装包括管芯焊盘; 安装在管芯焊盘上的半导体管芯; 沿着所述管芯焊盘的周缘设置的多个引线; 引线和芯片焊盘之间的接地棒; 以及将接地棒与管芯焊盘连接的多个桥，其中两个相邻桥之间的间隙具有等于或小于3mm的长度。

7. 发明授权

US08050129B2 E-fuse apparatus for controlling reference voltage required for programming/reading e-fuse macro in an integrated circuit via switch device in the same integrated circuit 有权
标题翻译：用于控制在同一集成电路中通过开关装置在集成电路中编程/读取电容保险丝宏需要的参考电压的电熔丝装置
公开(公告)号：US08050129B2
公开(公告)日：2011-11-01
申请号：US12491247
申请日：2009-06-25
申请人： Chia-Hsien Liu , Rei-Fu Huang , Chien-Chung Chen , Che-Yuan Jao
发明人： Chia-Hsien Liu , Rei-Fu Huang , Chien-Chung Chen , Che-Yuan Jao
IPC分类号： G11C7/00
CPC分类号： G04B37/0481 , G04B19/065
摘要： An electrically programmable fuse (e-fuse) apparatus includes an e-fuse macro and a switch device. The e-fuse macro is disposed in an integrated circuit, and has a plurality of e-fuse units. The switch device is disposed in the integrated circuit, and has an output node coupled to the e-fuse units and a first input node coupled to a first power source which supplies a first reference voltage acting as a programming voltage of the e-fuse macro. The switch device connects the first power source to the e-fuse units when the e-fuse macro is operated under a programming mode.
摘要翻译：电可编程保险丝（e-fuse）装置包括电子熔丝宏和开关装置。电子熔丝宏设置在集成电路中，并且具有多个电子熔丝单元。开关装置设置在集成电路中，并且具有耦合到电子熔丝单元的输出节点和耦合到第一电源的第一输入节点，第一电源提供充当电子熔丝宏的编程电压的第一参考电压。当在编程模式下操作电子熔丝宏时，开关装置将第一电源连接到电子熔丝单元。

8. 发明授权

US07741855B2 Calibration circuit for resistance component 有权
标题翻译：电阻元件校准电路
公开(公告)号：US07741855B2
公开(公告)日：2010-06-22
申请号：US12336491
申请日：2008-12-16
申请人： Che Yuan Jao
发明人： Che Yuan Jao
IPC分类号： G01R35/00 , H03K17/16 , G01P21/00
CPC分类号： H03H11/30 , H03H11/245 , H04L25/0278 , H04L25/0298
摘要： A calibration circuit including a plurality of first resistance components, a plurality of second resistance components, and a first feedback system is provided. The first feedback system selects M1 first resistance components and N1 second resistance components so that a first combination of the M1 first resistance components and the N1 second resistance components has a first predetermined relationship with the impedance of a first resistor. The first feedback system selects M2 first resistance components and N2 second resistance components so that a second combination of the M2 first resistance components and the N2 second resistance components has a second predetermined relationship with the impedance of the first resistor. Based on the values of M1, N1, M2, N2, and a target impedance, the first feedback system generates a first set of calibration signals for a plurality of third resistance components and generates a second set of calibration signals for a plurality of fourth resistance components.
摘要翻译：提供了包括多个第一电阻分量，多个第二电阻分量和第一反馈系统的校准电路。第一反馈系统选择M1第一电阻分量和N1第二电阻分量，使得M1第一电阻分量和N1第二电阻分量的第一组合与第一电阻器的阻抗具有第一预定关系。第一反馈系统选择M2第一电阻分量和N2第二电阻分量，使得M2第一电阻分量和N2第二电阻分量的第二组合与第一电阻器的阻抗具有第二预定关系。基于M1，N1，M2，N2和目标阻抗的值，第一反馈系统为多个第三电阻分量产生第一组校准信号，并产生用于多个第四电阻的第二组校准信号组件。

9. 发明申请

US20090184395A1 INPUT/OUTPUT (I/O) BUFFER 审中-公开
标题翻译：输入/输出（I / O）缓冲器
公开(公告)号：US20090184395A1
公开(公告)日：2009-07-23
申请号：US12018206
申请日：2008-01-23
申请人： Che-Yuan Jao
发明人： Che-Yuan Jao
IPC分类号： H01L29/86 , H02H3/08
CPC分类号： H01L27/0288
摘要： An I/O buffer including an I/O circuit, a pad and a pulling resistant device. The I/O circuit is for inputting or outputting a signal. The pulling resistant device has a plurality of resistant elements electrically connected between the I/O circuit and the pad, for forming a resistance value.
摘要翻译： I / O缓冲器包括I / O电路，焊盘和抗拉装置。 I / O电路用于输入或输出信号。抗拉装置具有电连接在I / O电路和焊盘之间的多个电阻元件，用于形成电阻值。

10. 发明申请

US20120326753A1 RECEIVING CIRCUITS FOR CORE CIRCUITS 有权
标题翻译：接收核心电路电路
公开(公告)号：US20120326753A1
公开(公告)日：2012-12-27
申请号：US13169467
申请日：2011-06-27
申请人： Che-Yuan Jao
发明人： Che-Yuan Jao
IPC分类号： H03K5/22
CPC分类号： H03K19/00 , H03K5/08 , H03K5/2472
摘要： A receiving circuit for a core circuit is provided and includes a first receiving-path unit. The first receiving-path unit is capable of receiving an input signal and outputting an output signal to the core circuit according to the input signal. The first receiving-path unit includes an input buffer which is capable of operating in a core power domain of the core circuit and receiving a first clamped signal. When a level of the input signal is substantially equal to or lower than a first predetermined voltage level, the input signal is passed to the input buffer to serve as the first clamped signal, and the input buffer is capable of outputting the output signal in the core power domain according to the first clamped signal. When the level of the input signal is higher than the first predetermined voltage level, the input signal is not passed to the input buffer.
摘要翻译：提供了一种用于核心电路的接收电路，并且包括第一接收路径单元。第一接收路径单元能够接收输入信号，并根据输入信号向核心电路输出输出信号。第一接收路径单元包括能够在核心电路的核心电源域中操作并接收第一钳位信号的输入缓冲器。当输入信号的电平基本上等于或低于第一预定电压电平时，输入信号被传递到输入缓冲器以用作第一钳位信号，并且输入缓冲器能够输出输出信号核心电源域根据第一个钳位信号。当输入信号的电平高于第一预定电压电平时，输入信号不会传递到输入缓冲器。

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