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1. 发明授权

US07230336B2 Dual damascene copper interconnect to a damascene tungsten wiring level 有权
标题翻译：双镶嵌铜互连到镶嵌钨布线层
公开(公告)号：US07230336B2
公开(公告)日：2007-06-12
申请号：US10338624
申请日：2003-01-07
申请人： Charlotte D Adams , Anthony K. Stamper
发明人： Charlotte D Adams , Anthony K. Stamper
IPC分类号： H01L29/40
CPC分类号： H01L21/76808 , H01L21/31053 , H01L21/31116 , H01L21/31138 , H01L21/76801 , H01L21/76804 , H01L21/76819 , H01L21/7684
摘要： A method and structure for fabricating a dual damascene copper interconnect which electrically contacts a damascene tungsten wiring level. The method forms a first layer on a semiconductor substrate, a silicon nitride layer on the first layer, and a silicon dioxide layer on the silicon nitride layer. The first layer includes damascene tungsten interconnect regions separated by insulative dielectric material. A continuous space is formed by etching two contact troughs through the silicon dioxide and silicon nitride layers to expose damascene tungsten interconnect regions, and by etching a top portion of the silicon dioxide layer between the two contact troughs. A reduced-height portion of the silicon dioxide layer remains between the two contact troughs. The continuous space is filled with damascene copper. The resulting dual damascene copper interconnect electrically contacts the exposed damascene tungsten interconnect regions.
摘要翻译：一种用于制造电接触镶嵌钨布线层的双镶嵌铜互连的方法和结构。该方法在半导体衬底上形成第一层，在第一层上形成氮化硅层，在氮化硅层上形成二氧化硅层。第一层包括由绝缘介电材料隔开的镶嵌钨互连区域。通过蚀刻通过二氧化硅和氮化硅层的两个接触槽来暴露镶嵌钨互连区域，并且通过在两个接触槽之间蚀刻二氧化硅层的顶部部分来形成连续空间。二氧化硅层的缩小部分保留在两个接触槽之间。连续的空间填充有镶嵌铜。所得到的双镶嵌铜互连件电接触暴露的镶嵌钨互连区域。

2. 发明申请

US20090179283A1 METAL GATE STACK AND SEMICONDUCTOR GATE STACK FOR CMOS DEVICES 有权
标题翻译：用于CMOS器件的金属栅极堆叠和半导体栅极堆叠
公开(公告)号：US20090179283A1
公开(公告)日：2009-07-16
申请号：US11954918
申请日：2007-12-12
申请人： Charlotte D. Adams , Bruce B. Doris , Philip Fisher , William K. Henson , Jeffrey W. Sleight
发明人： Charlotte D. Adams , Bruce B. Doris , Philip Fisher , William K. Henson , Jeffrey W. Sleight
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/4983 , H01L21/82345 , H01L21/823462 , H01L21/823468 , H01L21/823842 , H01L21/823857 , H01L21/823864 , H01L27/092 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/6656 , H01L29/78
摘要： A semiconductor gate stack comprising a silicon oxide based gate dielectric and a doped semiconductor material is formed on a semiconductor substrate. A high-k material metal gate electrode comprising a high-k gate dielectric and a metal gate portion is also formed on the semiconductor substrate. Oxygen-impermeable dielectric spacers are formed on the sidewalls of the semiconductor gate stack and the high-k material metal gate stack. The oxygen-impermeable dielectric spacer on the semiconductor gate stack is removed, while the oxygen impermeable dielectric spacer on the high-k material metal gate electrode is preserved. A low-k dielectric spacer is formed on the semiconductor gate stack, which provides a low parasitic capacitance for the device employing the semiconductor gate stack.
摘要翻译：包括基于氧化硅的栅极电介质和掺杂的半导体材料的半导体栅极堆叠形成在半导体衬底上。还在半导体衬底上形成包括高k栅极电介质和金属栅极部分的高k材料金属栅电极。在半导体栅极堆叠和高k材料金属栅极堆叠的侧壁上形成氧气不可渗透的电介质间隔物。除去半导体栅极堆叠上的不透氧电介质间隔物，同时保留高k材料金属栅电极上的不透氧电介质间隔物。在半导体栅极叠层上形成一个低k电介质隔离层，为采用半导体栅极堆叠的器件提供了低寄生电容。

3. 发明授权

US06566242B1 Dual damascene copper interconnect to a damascene tungsten wiring level 有权
标题翻译：双镶嵌铜互连到镶嵌钨布线层
公开(公告)号：US06566242B1
公开(公告)日：2003-05-20
申请号：US09816977
申请日：2001-03-23
申请人： Charlotte D. Adams , Anthony K. Stamper
发明人： Charlotte D. Adams , Anthony K. Stamper
IPC分类号： H01L214763
CPC分类号： H01L21/76808 , H01L21/31053 , H01L21/31116 , H01L21/31138 , H01L21/76801 , H01L21/76804 , H01L21/76819 , H01L21/7684
摘要： A method and structure for fabricating a dual damascene copper interconnect which electrically contacts a damascene tungsten wiring level. The method forms a first layer on a semiconductor substrate, a silicon nitride layer on the first layer, and a silicon dioxide layer on the silicon nitride layer. The first layer includes damascene tungsten interconnect regions separated by insulative dielectric material. A continuous space is formed by etching two contact troughs through the silicon dioxide and silicon nitride layers to expose damascene tungsten interconnect regions, and by etching a top portion of the silicon dioxide layer between the two contact troughs. A reduced-height portion of the silicon dioxide layer remains between the two contact troughs. The continuous space is filled with damascene copper. The resulting dual damascene copper interconnect electrically contacts the exposed damascene tungsten interconnect regions.
摘要翻译：一种用于制造电接触镶嵌钨布线层的双镶嵌铜互连的方法和结构。该方法在半导体衬底上形成第一层，在第一层上形成氮化硅层，在氮化硅层上形成二氧化硅层。第一层包括由绝缘介电材料隔开的镶嵌钨互连区域。通过蚀刻通过二氧化硅和氮化硅层的两个接触槽来暴露镶嵌钨互连区域，并且通过在两个接触槽之间蚀刻二氧化硅层的顶部部分来形成连续空间。二氧化硅层的缩小部分保留在两个接触槽之间。连续的空间填充有镶嵌铜。所得到的双镶嵌铜互连件电接触暴露的镶嵌钨互连区域。

4. 发明授权

US08030709B2 Metal gate stack and semiconductor gate stack for CMOS devices 有权
标题翻译： CMOS器件的金属栅极堆叠和半导体栅极堆叠
公开(公告)号：US08030709B2
公开(公告)日：2011-10-04
申请号：US11954918
申请日：2007-12-12
申请人： Charlotte D. Adams , Bruce B. Doris , Philip Fisher , William K. Henson , Jeffrey W. Sleight
发明人： Charlotte D. Adams , Bruce B. Doris , Philip Fisher , William K. Henson , Jeffrey W. Sleight
IPC分类号： H01L21/70 , H01L27/148 , H01L27/12 , H01L21/84 , H01L21/338
CPC分类号： H01L29/4983 , H01L21/82345 , H01L21/823462 , H01L21/823468 , H01L21/823842 , H01L21/823857 , H01L21/823864 , H01L27/092 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/6656 , H01L29/78
摘要： A semiconductor gate stack comprising a silicon oxide based gate dielectric and a doped semiconductor material is formed on a semiconductor substrate. A high-k material metal gate electrode comprising a high-k gate dielectric and a metal gate portion is also formed on the semiconductor substrate. Oxygen-impermeable dielectric spacers are formed on the sidewalls of the semiconductor gate stack and the high-k material metal gate stack. The oxygen-impermeable dielectric spacer on the semiconductor gate stack is removed, while the oxygen impermeable dielectric spacer on the high-k material metal gate electrode is preserved. A low-k dielectric spacer is formed on the semiconductor gate stack, which provides a low parasitic capacitance for the device employing the semiconductor gate stack.
摘要翻译：包括基于氧化硅的栅极电介质和掺杂的半导体材料的半导体栅极堆叠形成在半导体衬底上。还在半导体衬底上形成包括高k栅极电介质和金属栅极部分的高k材料金属栅电极。在半导体栅极堆叠和高k材料金属栅极堆叠的侧壁上形成氧气不可渗透的电介质间隔物。除去半导体栅极堆叠上的不透氧电介质间隔物，同时保留高k材料金属栅电极上的不透氧电介质间隔物。在半导体栅极叠层上形成一个低k电介质隔离层，为采用半导体栅极堆叠的器件提供了低寄生电容。

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