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1. 发明授权

US07610206B2 Provision of custom configured assemblies 有权
标题翻译：提供自定义配置的程序集
公开(公告)号：US07610206B2
公开(公告)日：2009-10-27
申请号：US10063814
申请日：2002-05-15
申请人： Charles Edward Kuhlmann , Francis E Noel, Jr. , Norman Clark Strole
发明人： Charles Edward Kuhlmann , Francis E Noel, Jr. , Norman Clark Strole
IPC分类号： G06Q10/00
CPC分类号： G06Q10/06
摘要： Provision to a customer of equipment already installed into a specified enclosure to create an assembly is accomplished in an advantageous manner by the disclosed process. A manufacturer obtains the enclosure and the components of the specified equipment, installs the equipment in the enclosure and performs appropriate tests on the completed assembly before sending the assembly to the customer.
摘要翻译：通过所公开的处理以有利的方式为已经安装到指定外壳中的设备的客户提供创建组件。制造商获得外壳和指定设备的组件，将设备安装在机柜中，并在将组件发送给客户之前对完成的组件进行适当的测试。

2. 发明授权

US07047464B2 Method and system for use of a field programmable function within an application specific integrated circuit (ASIC) to access internal signals for external observation and control 失效
公开(公告)号：US07047464B2
公开(公告)日：2006-05-16
申请号：US10016448
申请日：2001-12-10
申请人： Robert Thomas Bailis , Charles Edward Kuhlmann , Charles Steven Lingafelt , Ann Marie Rincon
发明人： Robert Thomas Bailis , Charles Edward Kuhlmann , Charles Steven Lingafelt , Ann Marie Rincon
IPC分类号： G01R31/28 , G06F17/50
CPC分类号： G01R31/318519
摘要： An application specific integrated circuit (ASIC) is disclosed. The ASIC includes a standard cell. The standard cell includes a plurality of logic functions. The ASIC also includes at least one bus coupled to at least a portion of the logic functions and a plurality of internal signals from the plurality of logic functions. Finally, the ASIC includes a field programmable (FP) function coupled to the at least one bus and at least a portion of the plurality of internal signals. The FP function provides access to internal signals for observation and control. An ASIC using a field programmable gate array (FPGA) function within a standard cell design is utilized to create an internal-to-the-ASIC bridging of internal signals to observe and control of the internal signals of the ASIC. By the placement of logic, which expresses a test program, into the FPGA function that manipulates the I/O pins and/or other functional entities of interest, the ASIC function and/or surrounding logic can be easily verified. In addition, through this system, internal and/or system (external-to-the-ASIC) conditions can be observed. Furthermore, a sequence of resets to different functional blocks can be executed utilizing a system and method in accordance with the present invention. Finally, through this system the end user of the ASIC could write their own error condition correction FPGA code which would communicate using protocols of the existing system error condition architecture.

3. 发明授权

US07347570B2 Multimedia presentation apparatus and method 失效
标题翻译：多媒体演示装置及方法
公开(公告)号：US07347570B2
公开(公告)日：2008-03-25
申请号：US10536039
申请日：2002-11-22
申请人： Charles Edward Kuhlmann , Francis Edward Noel, Jr. , Charles Joseph Sannipoli
发明人： Charles Edward Kuhlmann , Francis Edward Noel, Jr. , Charles Joseph Sannipoli
IPC分类号： G03B23/00 , G03B21/14 , G03B21/22 , G06T1/00 , G09G5/39 , G06F13/28 , G06F12/00 , H04N5/64
CPC分类号： H04N9/3141
摘要： A multimedia presentation apparatus and method by which a presenter is freed from the requirement of having or providing or transporting a supporting computer system such as the notebook or laptop system by the incorporation of computing capability and an accessible data port into the housing of the apparatus through which an executable data file may be delivered to cause generation of the desired presentation.
摘要翻译：一种多媒体呈现装置和方法，通过该演示装置和方法，通过将计算能力和可访问的数据端口并入设备的外壳中，可以免除具有或提供或传送诸如笔记本或膝上型计算机系统的支持计算机系统的要求，可执行数据文件可以被传送以引起所需呈现的产生。

4. 发明授权

US06806730B2 Method and system for use of an embedded field programmable gate array interconnect for flexible I/O connectivity 有权
标题翻译：使用嵌入式现场可编程门阵列互连的灵活I / O连接方法和系统
公开(公告)号：US06806730B2
公开(公告)日：2004-10-19
申请号：US10016772
申请日：2001-12-10
申请人： Robert Thomas Bailis , Charles Edward Kuhlmann , Charles Steven Lingafelt , Ann Marie Rincon
发明人： Robert Thomas Bailis , Charles Edward Kuhlmann , Charles Steven Lingafelt , Ann Marie Rincon
IPC分类号： G06F738
CPC分类号： G06F15/7867
摘要： An application specific integrated circuit (ASIC) is disclosed. The ASIC comprises a standard cell, the standard cell including a plurality of logic functions. The ASIC further includes at least one FPGA interconnect coupled to at least a portion of the logic functions. The FPGA interconnect can be configured to select a particular logic function of the plurality of logic functions. An ASIC in accordance with the present invention allows “field selection” of functions that are connected to the internal bus(es) and to external I/O. In addition, functional block connections made with internal buses can be significantly wider and faster than buses brought on chip via external chip I/Os. Further, the ASIC reduces cost because selective bus connections can be made internal to the chip, thus eliminating the need for external pins. Finally, the ASIC reduces the cost of the packaged component by allowing the chip to be packaged in a lower pin count package.
摘要翻译：公开了专用集成电路（ASIC）。 ASIC包括标准单元，标准单元包括多个逻辑功能。 ASIC还包括耦合到至少一部分逻辑功能的至少一个FPGA互连。 FPGA互连可以被配置为选择多个逻辑功能的特定逻辑功能。根据本发明的ASIC允许连接到内部总线和外部I / O的功能的“现场选择”。此外，内部总线的功能块连接可以比通过外部芯片I / O芯片上的总线显着更宽更快。此外，ASIC可以降低成本，因为可以在芯片内部进行选择性总线连接，因此不需要外部引脚。最后，ASIC通过将芯片封装成较低的引脚数封装来降低封装元件的成本。

5. 发明授权

US06754881B2 Field programmable network processor and method for customizing a network processor 失效
标题翻译：用于定制网络处理器的现场可编程网络处理器和方法
公开(公告)号：US06754881B2
公开(公告)日：2004-06-22
申请号：US10016346
申请日：2001-12-10
申请人： Charles Edward Kuhlmann , Charles Steven Lingafelt , Francis Edward Noel, Jr. , Ann Marie Rincon , Norman Clark Strole
发明人： Charles Edward Kuhlmann , Charles Steven Lingafelt , Francis Edward Noel, Jr. , Ann Marie Rincon , Norman Clark Strole
IPC分类号： G06F1750
CPC分类号： G06F15/7867 , G06F17/5054
摘要： A network processor is disclosed. The network processor comprises a plurality of standard cells; and at least one field programmable gate array (FPGA) cell that can communicate with at least one of the standard cells. The at least one FPGA cell can provide a specified function based upon field programming techniques to allow for customization of the network processor. Utilizing a method and system in accordance with the present invention, a network processor can be customized to implement a variety of functions in hardware using embedded FPGA macros. The combined technology of ASIC standard cells plus FPGA cells enables fast time-to-market for new designs while optimizing cost and performance. In addition, the combined ASIC plus FPGA on a single die allows the chip developer to use proven standard cell macros for common logic and programmable cells for high-risk logic. Through a system and method in accordance with the present invention a business process is also provided whereby an ASIC customer can either submit a custom logic file to a vendor or choose from a library of functions to program into the FPGA portion of the chip.
摘要翻译：公开了一种网络处理器。网络处理器包括多个标准单元; 以及可以与至少一个标准单元通信的至少一个现场可编程门阵列（FPGA）单元。至少一个FPGA单元可以基于现场编程技术提供指定的功能，以允许对网络处理器的定制。利用根据本发明的方法和系统，可以定制网络处理器以使用嵌入式FPGA宏来实现硬件中的各种功能。 ASIC标准单元与FPGA单元的组合技术可实现新设计的快速上市，同时优化成本和性能。此外，单芯片上的组合ASIC加上FPGA允许芯片开发人员使用经验证的标准单元宏用于通用逻辑和可编程单元，用于高风险逻辑。通过根据本发明的系统和方法，还提供了一种业务处理，其中ASIC客户可以向供应商提交自定义逻辑文件或者从功能库中选择来编程到芯片的FPGA部分。

6. 发明授权

US06668361B2 Method and system for use of a field programmable function within a chip to enable configurable I/O signal timing characteristics 有权
公开(公告)号：US06668361B2
公开(公告)日：2003-12-23
申请号：US10015920
申请日：2001-12-10
申请人： Robert Thomas Bailis , Charles Edward Kuhlmann , Charles Steven Lingafelt , Ann Marie Rincon
发明人： Robert Thomas Bailis , Charles Edward Kuhlmann , Charles Steven Lingafelt , Ann Marie Rincon
IPC分类号： G06F1750
CPC分类号： G06F17/5054
摘要： An application specific integrated circuit (ASIC) is disclosed. The ASIC includes a standard cell, the standard cell including a plurality of logic functions. The ASIC also includes an input/output (I/O) configuration function coupled to at least a portion of the logic functions. The ASIC further includes a field programmable gate array (FPGA) function coupled to the I/O configuration function. The FPGA function controls the I/O configuration function based upon a configuration file. A system in accordance with the present invention reduces the cost and time associated with the timing analysis activities during development. An FPGA function within the ASIC is utilized to control the I/O characteristics such as delay, termination and/or slew rate for the I/O pin mapping. Different I/O configurations will be provided by the FPGA function depending on the environment the ASIC is used in. By providing an ASIC that is adaptable to different timing criteria through FPGA programming, the timing analysis performed by the user of the ASIC will be substantially reduced, resulting in a reduction of the development cycle.

7. 发明授权

US07171505B2 Universal network interface connection 失效
标题翻译：通用网络接口连接
公开(公告)号：US07171505B2
公开(公告)日：2007-01-30
申请号：US10137167
申请日：2002-05-02
申请人： Charles Edward Kuhlmann , Francis Edward Noel, Jr. , Ann Marie Rincon , Rosemary Venema Slager , Norman Clark Strole
发明人： Charles Edward Kuhlmann , Francis Edward Noel, Jr. , Ann Marie Rincon , Rosemary Venema Slager , Norman Clark Strole
IPC分类号： G06F13/14
CPC分类号： G06F13/4022 , G06F13/387
摘要： An interface connection is described for joining a host device, such as a Network Processor, to peripherals such as modems, printers, local area networks, Ethernets and Token-Ring interfaces. The connection is particularly useful for joining portable computers, such as laptops, to these peripherals. The connector utilizes a programmable Network Processor (NP) either in the host device or in an external fan-out box. This programmable Network Processor adapts the host device to a variety of peripheral devices utilizing different protocols and I/O speeds. The NP can use a Digital Signal Processor to provide programmable services to the physical layers. The host device may contain a high-speed communication interface with the NP contained in the external connection box.
摘要翻译：描述了用于将诸如网络处理器的主机设备连接到诸如调制解调器，打印机，局域网，以太网和令牌环接口的外围设备的接口连接。该连接对于将诸如笔记本电脑的便携式计算机连接到这些外围设备是特别有用的。连接器在主机设备或外部扇出盒中使用可编程网络处理器（NP）。该可编程网络处理器使用不同的协议和I / O速度将主机设备适配到各种外围设备。 NP可以使用数字信号处理器为物理层提供可编程服务。主机设备可能包含与外部连接盒中包含的NP的高速通信接口。

8. 发明授权

US06593771B2 Method and system for use of a field programmable interconnect within an ASIC for configuring the ASIC 有权
标题翻译：用于ASIC内的现场可编程互连的配置方法和系统
公开(公告)号：US06593771B2
公开(公告)日：2003-07-15
申请号：US10015922
申请日：2001-12-10
申请人： Robert Thomas Bailis , Charles Edward Kuhlmann , Charles Steven Lingafelt , Ann Marie Rincon
发明人： Robert Thomas Bailis , Charles Edward Kuhlmann , Charles Steven Lingafelt , Ann Marie Rincon
IPC分类号： G06F738
CPC分类号： G06F15/7867
摘要： An integrated circuit comprising a standard cell is disclosed. The standard cell includes a plurality of logic functions; at least a portion of the logic functions requiring initialization. The circuit includes a field programmable gate array (FPGA) cell coupled to the at least a portion of the plurality of logic functions. The at least a portion of the plurality of logic functions are initialized by the FPGA cell. In a method and system in accordance with the present invention, an on-chip Field Programmable Gate Array (FPGA) cell is configured to implement the required application-specific function initializations. The FPGA cell could be wired directly to each of the registers within the functional blocks requiring initialization. These registers would also be wired to the processor bus allowing software access for normal operation after initialization. Access to these registers can be controlled by a simple muxing structure that allows the FPGA to have direct access to the registers when the chip initialization sequence takes place (Chip_Init signal is asserted) and allows the processor bus to have access after initialization is complete (Chip_Init signal is de-asserted).
摘要翻译：公开了一种包括标准单元的集成电路。标准单元包括多个逻辑功能; 逻辑功能的至少一部分需要初始化。电路包括耦合到多个逻辑功能的至少一部分的现场可编程门阵列（FPGA）单元。多个逻辑功能的至少一部分由FPGA单元初始化。在根据本发明的方法和系统中，片上现场可编程门阵列（FPGA）单元被配置为实现所需的应用特定功能初始化。 FPGA单元可以直接连接到需要初始化的功能块内的每个寄存器。这些寄存器也将连接到处理器总线，允许在初始化后进行正常操作的软件访问。这些寄存器的访问可以通过简单的多路复用结构进行控制，允许FPGA在芯片初始化序列发生时直接访问寄存器（Chip_Init信号被断言），并允许处理器总线在初始化完成后进入（Chip_Init 信号被取消断言）。

9. 发明授权

US06545501B1 Method and system for use of a field programmable function within a standard cell chip for repair of logic circuits 失效
标题翻译：在标准单元芯片内使用现场可编程功能来修复逻辑电路的方法和系统
公开(公告)号：US06545501B1
公开(公告)日：2003-04-08
申请号：US10015923
申请日：2001-12-10
申请人： Robert Thomas Bailis , Charles Edward Kuhlmann , Charles Steven Lingafelt , Ann Marie Rincon
发明人： Robert Thomas Bailis , Charles Edward Kuhlmann , Charles Steven Lingafelt , Ann Marie Rincon
IPC分类号： H03K19003
CPC分类号： H03K19/177
摘要： An application specific integrated circuit (ASIC) is disclosed. The ASIC comprises a standard cell. The standard cell includes a plurality of logic functions. The ASIC further includes a field programmable (FP) logic function for coupling the plurality of logic functions together via a plurality of input and output stages. The FP logic function can be programmed for field repair of at least one of the plurality of the logic functions. A method and system in accordance with the present invention utilizes a distributed field programmable logic block in conjunction with standard cells to provide for field repair and improved redundancy. To describe the features of the present invention in more detail, refer now to the following description in conjunction with the accompanying drawings.
摘要翻译：公开了专用集成电路（ASIC）。 ASIC包括标准单元。标准单元包括多个逻辑功能。 ASIC还包括用于经由多个输入和输出级将多个逻辑功能耦合在一起的现场可编程（FP）逻辑功能。 FP逻辑功能可以被编程用于多个逻辑功能中的至少一个的现场修复。根据本发明的方法和系统利用分布式现场可编程逻辑块结合标准单元来提供现场修复和改进的冗余。为了更详细地描述本发明的特征，现在结合附图参考下面的描述。

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