专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4475118A Dynamic MOS RAM with storage cells having a mainly insulated first plate 失效
标题翻译：具有存储单元的动态MOS RAM具有主要绝缘的第一板
公开(公告)号：US4475118A
公开(公告)日：1984-10-02
申请号：US217425
申请日：1980-12-15
申请人： Thomas Klein , Charles E. Boettcher
发明人： Thomas Klein , Charles E. Boettcher
IPC分类号： H01L27/108 , H01L27/04 , G11C11/40
CPC分类号： H01L27/10805
摘要： An improved dynamic MOS RAM having a plurality of selection lines and data lines and a plurality of storage cells connected thereto, wherein each storage cell includes a storage capacitor having first and second plates, wherein the second plate is adapted to be coupled to a reference potential terminal; and a MOSFET having a semiconductor substrate, a gate connected to one of the selection lines, a first conduction terminal coupled to one of the data lines, and a second conduction terminal connected in common with a first plate of the storage capacitor, is disclosed. The first plate of the storage capacitor includes first doped polysilicon conductive layer that has the majority of its area separated from the semiconductor substrate of the MOSFET by at least an insulating layer. The second plate of the storage capacitor includes a second doped polysilicon conductive layer that is at least coextensive with and insulated from the first conductive layer. The transistor gate is defined by a third doped polysilicon conductive layer that is insulated from the first and second conductive layers. Approximately 45% of the cell area can be utilized for charge storage, and only about 20% of this storage area is susceptible to loss of charge by reason of leakage through the depletion/junction area in the substrate.
摘要翻译：一种改进的动态MOS RAM，具有多个选择线和数据线以及连接到其上的多个存储单元，其中每个存储单元包括具有第一和第二板的存储电容器，其中第二板适于耦合到参考电位终奌站; 以及具有半导体衬底的MOSFET，连接到选择线之一的栅极，耦合到数据线之一的第一导电端子和与存储电容器的第一板共同连接的第二导电端子。存储电容器的第一板包括第一掺杂多晶硅导电层，其第一掺杂多晶硅导电层的绝大部分区域通过至少绝缘层与MOSFET的半导体衬底分离。存储电容器的第二板包括与第一导电层至少共同延伸并与其绝缘的第二掺杂多晶硅导电层。晶体管栅极由与第一和第二导电层绝缘的第三掺杂多晶硅导电层限定。大约45％的电池区域可以用于电荷存储，并且由于通过衬底中的耗尽/结合区域的泄漏，该存储区域的约20％容易损失电荷。

2. 发明授权

US4290186A Method of making integrated semiconductor structure having an MOS and a capacitor device 失效
公开(公告)号：US4290186A
公开(公告)日：1981-09-22
申请号：US059637
申请日：1979-07-23
申请人： Thomas Klein , Andrew G. Varadi , Charles E. Boettcher
发明人： Thomas Klein , Andrew G. Varadi , Charles E. Boettcher
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/94 , B01J17/00 , H01L21/265
CPC分类号： H01L27/1085 , H01L27/10805 , H01L29/94
摘要： This disclosure is directed to an improved semiconductor capacitor structure especially useful in an integrated semiconductor structure with an MOS device and fabrication methods therefor. This semiconductor capacitor is particularly useful for forming the capacitor portion of a single MOS memory cell structure in a dynamic MOS random access memory which utilizes one MOS device in combination with a capacitor. In one specific disclosure embodiment, the semiconductor capacitor comprises a boron (P) implanted region in a substrate of P- type conductivity followed by a shallow arsenic (N) implant into the boron implanted region. The boron implanted region provides a P type conductivity which has a higher concentration of P type impurities than the concentration of impurities contained in the substrate which is of P- type conductivity. Thus, the boron implanted region performs the important function of preventing a surface N type inversion layer from being formed across the semiconductor surface beneath the silicon dioxide insulating layer which could occur across the substrate P- surface if the arsenic implant region was made into the P- substrate without the P type boron implant. The arsenic implant is of N type conductivity and has a higher concentration of impurities than the boron implant region. The dielectric portion of the semiconductor capacitor is the portion of the silicon dioxide layer located on the surface of the arsenic implanted region. A doped polysilicon electrode is formed over this portion of the silicon dioxide insulating layer and provides the other plate of the capacitor structure. In another embodiment that is disclosed, this above described semiconductor capacitor structure or device is combined with an MOS device in a single integrated semiconductor structure in order to provide a single MOS memory cell for dynamic random access memory chip utilizing the MOS device and the capacitor. Preferably, the semiconductor capacitor is shown as a connected extension of either the source or drain region of the MOS device.

3. 发明授权

US4272774A Self-aligned floating gate memory cell and method of manufacture 失效
标题翻译：自对准浮栅存储单元及其制造方法
公开(公告)号：US4272774A
公开(公告)日：1981-06-09
申请号：US59235
申请日：1979-07-19
申请人： Charles E. Boettcher
发明人： Charles E. Boettcher
IPC分类号： H01L21/033 , H01L21/28 , H01L29/788 , H01L29/78
CPC分类号： H01L21/033 , H01L21/28273 , H01L29/7881
摘要： A floating gate memory cell has its control gate self-aligned to the floating gate in the source to drain direction and its floating gate self-aligned to the channel region in that direction and the direction transverse thereto without overlaying the field oxide. The cell may be manufactured by the following method: forming insulation such as silicon oxide over the substrate to serve as gate oxide; forming a conductor such as polysilicon over the insulation; etching the polysilicon to a patterned mask and using the mask to dissolve the unprotected oxide to leave a future floating gate of polysilicon overlaying and coextensive with the future channel region in the direction transverse to the source-to-drain region; overlaying insulation such as a further oxide and then overlaying a second conductor such as polysilicon, which is thus insulated from the floating gate; patterning this second polysilicon, which will serve as a control gate, with a photo resist mask to etch the second conductor to form a control gate, and to preferentially remove enough oxide to expose the unmasked portion of the future floating gate, and etching this unmasked portion. Thus, the floating gate is self-aligned to the channel in the source-to-drain direction, as well as in the direction transverse to the source-to-drain direction. The remaining insulation may now be dissolved using the gates as masks to expose the source and drain regions.
摘要翻译：浮置栅极存储单元的控制栅极与源极 - 漏极方向上的浮置栅极自对准，并且其浮置栅极在该方向上与沟道区域自由对准，并且横向于沟道区域而不叠置场氧化物。电池可以通过以下方法制造：在衬底上形成诸如氧化硅的绝缘体以用作栅极氧化物; 在绝缘体上形成诸如多晶硅的导体; 将多晶硅蚀刻到图案化掩模，并使用掩模来溶解未受保护的氧化物，以留下未来的沟道区域在横向于源极 - 漏极区域的方向上覆盖并与之共同延伸的多晶硅的浮置栅极; 覆盖绝缘，例如另外的氧化物，然后覆盖由此与浮动栅极绝缘的第二导体，例如多晶硅; 使用第二多晶硅（其将用作控制栅极）将光致抗蚀剂掩模图案化以蚀刻第二导体以形成控制栅极，并优先去除足够的氧化物以暴露未来浮栅的未屏蔽部分，并蚀刻该未屏蔽的一部分。因此，浮置栅极在源极到漏极方向以及横向于源极 - 漏极方向的方向上自对准到沟道。剩余的绝缘材料现在可以使用栅极作为掩模溶解以暴露出源区和漏区。

4. 发明授权

US4413401A Method for making a semiconductor capacitor 失效
公开(公告)号：US4413401A
公开(公告)日：1983-11-08
申请号：US280984
申请日：1981-07-06
申请人： Thomas Klein , Andrew G. Varadi , Charles E. Boettcher
发明人： Thomas Klein , Andrew G. Varadi , Charles E. Boettcher
IPC分类号： H01L21/8234 , H01L27/108 , H01L29/94 , B01J17/00 , H01L21/265
CPC分类号： H01L21/8234 , H01L27/10805 , H01L29/94
摘要： This disclosure is directed to an improved semiconductor capacitor structure especially useful in an integrated semiconductor structure with an MOS device and fabrication methods therefor. This semiconductor capacitor is particularly useful for forming the capacitor portion of a single MOS memory cell structure in a dynamic MOS random access memory which utilizes one MOS device in combination with a capacitor. In one specific disclosure embodiment, the semiconductor capacitor comprises a boron (P) implanted region in a substrate of P- type conductivity followed by a shallow arsenic (N) implant into the boron implanted region. The boron implanted region provides a P type conductivity which has a higher concentration of P type impurities than the concentration of impurities contained in the substrate which is of P- type conductivity. Thus, the boron implanted region performs the important function of preventing a surface N type inversion layer from being formed across the semiconductor surface beneath the silicon dioxide insulating layer which could occur across the substrate P- surface if the arsenic implant region was made into the P- substrate without the P type boron implant. The arsenic implant is of N type conductivity and has a higher concentration of impurities than the boron implant region. The dielectric portion of the semiconductor capacitor is the portion of the silicon dioxide layer located on the surface of the arsenic implanted region. A doped polysilicon electrode is formed over this portion of the silicon dioxide insulating layer and provides the other plate of the capacitor structure. In another embodiment that is disclosed, this above described semiconductor capacitor structure or device is combined with an MOS device in a single integrated semiconductor structure in order to provide a single MOS memory cell for dynamic random access memory chip utilizing the MOS device and the capacitor. Preferably, the semiconductor capacitor is shown as a connected extension of either the source or drain region of the MOS device.

5. 发明授权

US4355455A Method of manufacture for self-aligned floating gate memory cell 失效
标题翻译：自对准浮栅存储单元的制造方法
公开(公告)号：US4355455A
公开(公告)日：1982-10-26
申请号：US207653
申请日：1980-11-17
申请人： Charles E. Boettcher
发明人： Charles E. Boettcher
IPC分类号： H01L21/033 , H01L21/28 , H01L29/788 , H01L21/22
CPC分类号： H01L21/033 , H01L21/28273 , H01L29/7881
摘要： A floating gate memory cell has its control gate self-aligned to the floating gate in the source to drain direction and its floating gate self-aligned to the channel region in that direction and the direction transverse thereto without overlaying the field oxide. The cell may be manufactured by the following method: forming insulation such as silicon oxide over the substrate to serve as gate oxide; forming a conductor such as polysilicon over the insulation; etching the polysilicon to a patterned mask and using the mask to dissolve the unprotected oxide to leave a future floating gate of polysilicon overlaying and coextensive with the future channel region in the direction transverse to the source-to-drain region; overlaying insulation such as a further oxide and then overlaying a second conductor such as polysilicon, which is thus insulated from the floating gate; patterning this second polysilicon, which will serve as a control gate, with a photo resist mask to etch the second conductor to form a control gate, and to preferentially remove enough oxide to expose the unmasked portion of the future floating gate, and etching this unmasked portion. Thus, the floating gate is self-aligned to the channel in the source-to-drain direction, as well as in the direction transverse to the source-to-drain direction. The remaining insulation may now be dissolved using the gates as masks to expose the source and drain regions.
摘要翻译：浮置栅极存储单元的控制栅极与源极 - 漏极方向上的浮置栅极自对准，并且其浮置栅极在该方向上与沟道区域自由对准，并且横向于沟道区域而不叠置场氧化物。电池可以通过以下方法制造：在衬底上形成诸如氧化硅的绝缘体以用作栅极氧化物; 在绝缘体上形成诸如多晶硅的导体; 将多晶硅蚀刻到图案化掩模，并使用掩模来溶解未受保护的氧化物，以留下未来的沟道区域在横向于源极 - 漏极区域的方向上覆盖并与之共同延伸的多晶硅的浮置栅极; 覆盖绝缘，例如另外的氧化物，然后覆盖由此与浮动栅极绝缘的第二导体，例如多晶硅; 使用第二多晶硅（其将用作控制栅极）将光致抗蚀剂掩模图案化以蚀刻第二导体以形成控制栅极，并优先去除足够的氧化物以暴露未来浮栅的未屏蔽部分，并蚀刻该未屏蔽的一部分。因此，浮置栅极在源极到漏极方向以及横向于源极 - 漏极方向的方向上自对准到沟道。剩余的绝缘材料现在可以使用栅极作为掩模溶解以暴露出源区和漏区。

6. 发明授权

US4216386A Charge coupled device with reduced power consumption upon charge transfer 失效
标题翻译：电荷耦合器件，在电荷转移时具有降低的功耗
公开(公告)号：US4216386A
公开(公告)日：1980-08-05
申请号：US5994
申请日：1979-01-24
申请人： Charles E. Boettcher
发明人： Charles E. Boettcher
IPC分类号： G11C19/28 , H01L29/768 , H01L29/78
CPC分类号： H01L29/76891 , G11C19/285
摘要： A charge coupled device is controlled to conserve energy during charge transfer. By connecting the storage electrode corresponding to the substrate region in which a charge packet is stored to an adjacent electrode, the potential at the storage electrode is reduced and the potential on the adjacent electrode is increased to a level where charge transfer is initiated to transfer a portion of the charge packet to the substrate region corresponding to the next adjacent storage electrode.
摘要翻译：控制电荷耦合器件以在电荷转移期间节省能量。通过将对应于其中存储有电荷分组的衬底区域的存储电极连接到相邻电极，存储电极处的电位降低，并且相邻电极上的电位增加到电荷转移开始以转移电荷分组的一部分到对应于下一相邻存储电极的衬底区域。

7. 发明授权

US4069474A MOS Dynamic random access memory having an improved sensing circuit 失效
标题翻译： MOS具有改进的感测电路的动态随机存取存储器
公开(公告)号：US4069474A
公开(公告)日：1978-01-17
申请号：US677462
申请日：1976-04-15
申请人： Charles E. Boettcher , Joel A. Karp , John A. Reed , Andrew G. Varadi
发明人： Charles E. Boettcher , Joel A. Karp , John A. Reed , Andrew G. Varadi
IPC分类号： G11C11/404 , G11C11/4091 , H03K3/356 , G11C7/06 , G11C11/24 , G11C11/40
CPC分类号： G11C11/4091 , G11C11/404 , H03K3/356017 , H03K3/35606 , H03K3/356095
摘要： In a memory circuit, first and second bit line portions, each having a plurality of memory cells coupled thereto are provided for reading and writing electrical potentials into and out of the coupled memory cells. A bistable flip-flop type sensing amplifier is coupled between the first and second bit portion for sensing the voltage difference therebetween and for latching into one of the two states in response to sensing either a "0" or a "1" accessed to one of the bit line portions from an addressed memory cell to be read out of the memory. A high input impedance amplifier is provided between the respective bit line portion and the respective input terminal of the sensing amplifier for isolating (buffering) the stray capacitance of the sensing amplifier circuit from the capacitance of its bit line. Switchable restore circuitry bypasses each of the isolating line amplifiers for the purposes of restoring electrical potentials read out of the addressed memory cells. In a preferred embodiment, the buffer line amplifiers comprise source follower amplifiers.
摘要翻译：在存储器电路中，提供每个具有与其耦合的多个存储单元的第一和第二位线部分，用于将电位读入和写入耦合的存储单元。双稳态触发器型感测放大器耦合在第一和第二位部分之间，用于感测其间的电压差，并且响应于感测到访问到“0”或“1”之一的“0”或“1”来锁存到两个状态之一来自寻址的存储器单元的位线部分将从存储器读出。在相应的位线部分和感测放大器的相应输入端之间提供高输入阻抗放大器，用于将感测放大器电路的寄生电容与其位线的电容隔离（缓冲）。可切换的恢复电路绕过每个隔离线路放大器，以恢复从寻址的存储单元读出的电位。在优选实施例中，缓冲线路放大器包括源极跟随放大器。

8. 发明授权

US4069475A MOS Dynamic random access memory having an improved sense and restore circuit 失效
标题翻译： MOS具有改进的感测和恢复电路的动态随机存取存储器
公开(公告)号：US4069475A
公开(公告)日：1978-01-17
申请号：US677463
申请日：1976-04-15
申请人： Charles E. Boettcher
发明人： Charles E. Boettcher
IPC分类号： G11C11/419 , G11C11/404 , G11C11/409 , G11C11/4091 , G11C7/06 , G11C11/24 , G11C11/40
CPC分类号： G11C11/404 , G11C11/4091
摘要： In a memory circuit, first and second bit line portions, each having a plurality of memory cells coupled thereto as provided for reading and writing electrical potentials into and out of the coupled memory cells. A bistable flip-flop type sensing amplifier is coupled between the first and second bit portion for sensing the voltage difference therebetween and for latching into one of the two states in response to sensing either a "0" or a "1" accessed to one of the bit line portions from an addressed memory cell to be read out of the memory. A high input impedance amplifier is provided between the respective bit line portion and the respective input terminal of the sensing amplifier for isolating (buffering) the stray capacitance of the sensing amplifier circuit from the capacitance of its bit line. Switchable restore circuitry bypasses each of the isolating line amplifiers for the purposes of restoring electrical potentials read out of the addressed memory cells. The restore timing signals for controlling the restore circuitry is derived from one of the outputs of the flip-flop sense amplifier so that the restore circuitry is self-timing and in addition power dissipation of the circuit is reduced because the time during which the bistable flip-flop draws signal current through the ON side thereof is reduced.
摘要翻译：在存储器电路中，第一和第二位线部分，每个都具有耦合到其上的多个存储器单元，用于将电势读入和写入到耦合的存储器单元中。双稳态触发器型感测放大器耦合在第一和第二位部分之间，用于感测其间的电压差，并且响应于感测到访问到“0”或“1”之一的“0”或“1”来锁存到两个状态之一来自寻址的存储器单元的位线部分将从存储器读出。在相应的位线部分和感测放大器的相应输入端之间提供高输入阻抗放大器，用于将感测放大器电路的寄生电容与其位线的电容隔离（缓冲）。可切换的恢复电路绕过每个隔离线路放大器，以恢复从寻址的存储单元读出的电位。用于控制恢复电路的恢复定时信号是从触发器读出放大器的输出之一导出的，使得恢复电路是自定时的，此外，电路的功耗被减小，因为双稳态翻转 - 通过其ON侧的信号电流减小。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式