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1. 发明授权

US08490030B1 Distance metric for accurate lithographic hotspot classification using radial and angular functions 有权
标题翻译：使用径向和角度函数的精确光刻热点分类的距离度量
公开(公告)号：US08490030B1
公开(公告)日：2013-07-16
申请号：US13487047
申请日：2012-06-01
申请人： Charles C. Chiang , Jing Guo , Fan Yang , Subarnarekha Sinha , Xuan Zeng
发明人： Charles C. Chiang , Jing Guo , Fan Yang , Subarnarekha Sinha , Xuan Zeng
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5081
摘要： An dual function distance metric for pattern matching based hotspot clustering is described. The dual function distance metric can handle patterns containing multiple polygons, is easy to compute, and is tolerant of small variations or shifts of the shapes. Compared with an XOR distance metric pattern clustering, the dual function distance metric can achieve up to 37.5% accuracy improvement with 2X-4X computational cost in the context of cluster analysis. The dual function distance metric is reliable and accurate for characterizing clips (e.g. hotspots), thereby making it desirable for industry applications.
摘要翻译：描述了基于模式匹配的热点聚类的双功能距离度量。双功能距离度量可以处理包含多个多边形的图案，易于计算，并且容忍形状的小变化或偏移。与XOR距离度量模式聚类相比，双重功能距离度量可以在聚类分析的上下文中使用2X-4X计算成本实现高达37.5％的精度提高。双功能距离度量对于表征剪辑（例如热点）是可靠和准确的，从而使其对于工业应用是理想的。

2. 发明授权

US08452075B2 Range pattern matching for hotspots containing vias and incompletely specified range patterns 有权
标题翻译：包含通孔和不完全指定范围模式的热点的范围模式匹配
公开(公告)号：US08452075B2
公开(公告)日：2013-05-28
申请号：US11786683
申请日：2007-04-11
申请人： Jingyu Xu , Subarnarekha Sinha , Charles C. Chiang
发明人： Jingyu Xu , Subarnarekha Sinha , Charles C. Chiang
IPC分类号： G06K9/00
CPC分类号： G06K9/469 , G06K2209/19 , G06T7/0006 , G06T7/12 , G06T2207/30141
摘要： One embodiment of the present invention provides a system that identifies hotspot areas in a layout. The system receives the layout and a via range pattern which indicates one or more vias and performs range-pattern matching (RPM) on the layout based on a via-free range pattern derived from the via range pattern. The system further identifies at least one candidate area and determines whether via(s) in the candidate area matches the via(s) in the via range pattern. The system can also receives a range pattern with don't care regions. The system determines a core pattern from the range pattern, performs RPM based on the core pattern, and identifies a candidate area. The system then determines whether areas surrounding the candidate area match a non-core effective pattern of the range pattern. The system further determines if the areas surrounding the candidate area satisfy the constraints associated with any vias and the don't care regions.
摘要翻译：本发明的一个实施例提供一种识别布局中的热点区域的系统。系统接收布局和指示一个或多个通孔的通孔范围图案，并且基于从通孔范围图案导出的无通孔范围图案在布局上执行范围图案匹配（RPM）。系统还识别至少一个候选区域并确定候选区域中的通路是否与通孔范围图案中的通孔匹配。系统也可以接收范围模式与不关心的区域。系统从范围模式确定核心模式，基于核心模式执行RPM，并识别候选区域。然后，系统确定候选区域周围的区域是否匹配范围模式的非核心有效模式。系统还确定候选区域周围的区域是否满足与任何通孔和无关区域相关联的限制。

3. 发明授权

US08209639B2 Identifying layout regions susceptible to fabrication issues by using range patterns 有权
标题翻译：通过使用范围模式识别易受制造问题影响的布局区域
公开(公告)号：US08209639B2
公开(公告)日：2012-06-26
申请号：US12362721
申请日：2009-01-30
申请人： Subarnarekha Sinha , Hailong Yao , Charles C. Chiang
发明人： Subarnarekha Sinha , Hailong Yao , Charles C. Chiang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A range pattern is matched to a block of an IC layout by slicing the layout block and the range pattern, followed by comparing a sequence of widths of layout slices to a sequence of width ranges of pattern slices and if the width of any layout slice falls outside the width range of a corresponding pattern slice then the layout block does not match the range pattern. If the comparison succeeds, further comparisons are made between a sequence of lengths of layout fragments in each layout slice and a sequence of length ranges of pattern fragments in corresponding pattern slices. If the length of any layout fragment falls outside the length range of a corresponding pattern fragment then the block does not match the range pattern. If all lengths are within their respective ranges, then the block matches the pattern, although additional constraints are checked in some embodiments.
摘要翻译：范围模式通过对布局块和范围模式进行切片来匹配IC布局块，然后将布局片段的宽度序列与模式片段的宽度范围序列进行比较，如果任何布局片段的宽度下降在对应的图案切片的宽度范围之外，则布局块与范围图案不匹配。如果比较成功，则在每个布局切片中的布局片段的长度序列和相应图案片段中的片段片段的长度范围的序列之间进行进一步的比较。如果任何布局片段的长度落在相应图案片段的长度范围之外，则该块与范围模式不匹配。如果所有长度在其各自的范围内，则块在匹配模式时，尽管在一些实施例中检查了附加的约束。

4. 发明授权

US08000826B2 Predicting IC manufacturing yield by considering both systematic and random intra-die process variations 有权
标题翻译：通过考虑系统和随机的模内工艺变化来预测IC制造产量
公开(公告)号：US08000826B2
公开(公告)日：2011-08-16
申请号：US11339184
申请日：2006-01-24
申请人： Jianfeng Luo , Subarnarekha Sinha , Qing Su , Charles C. Chiang
发明人： Jianfeng Luo , Subarnarekha Sinha , Qing Su , Charles C. Chiang
IPC分类号： G06F11/00 , G06F19/00 , G05B11/01 , H01L23/58 , G06K9/00
CPC分类号： G05B19/41875 , G05B2219/32204 , G05B2219/35142 , G05B2219/45031 , Y02P90/22
摘要： One embodiment of the present invention provides a system that predicts manufacturing yield for a die within a semiconductor wafer. During operation, the system first receives a physical layout of the die. Next, the system partitions the die into an array of tiles. The system then computes systematic variations for a quality indicative value to describe a process parameter across the array of tiles based on the physical layout of the die. Next, the system applies a random variation for the quality indicative parameter to each tile in the array of tiles. Finally, the system obtains the manufacturing yield for the die based on both the systematic variations and the random variations.
摘要翻译：本发明的一个实施例提供了一种系统，其预测半导体晶片内的管芯的制造成品率。在操作期间，系统首先接收模具的物理布局。接下来，系统将模具分割成瓦片阵列。然后，该系统计算质量指示值的系统变化，以基于模具的物理布局描述整个瓦片阵列上的过程参数。接下来，系统将质量指示参数的随机变量应用于瓦片阵列中的每个瓦片。最后，系统基于系统变化和随机变量得到了模具的制造成品率。

5. 发明授权

US07823099B2 Lithography suspect spot location and scoring system 有权
标题翻译：平版摄影怀疑现场位置和得分系统
公开(公告)号：US07823099B2
公开(公告)日：2010-10-26
申请号：US11756596
申请日：2007-05-31
申请人： Min-Chun Tsai , Charles C. Chiang
发明人： Min-Chun Tsai , Charles C. Chiang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A fast method to detect hot spots using foundry independent models that do not require RET/OPC synthesis is presented. In some embodiments of the present invention, sensitive spots are located. Lithography models are used to simulate the geometry near the sensitive spots to produce a model of the area around the sensitive spots. The sensitive spots are scored using a measure such as intensity (of light) or scoring based on contrast.
摘要翻译：提出了一种使用不需要RET / OPC合成的代工独立模型来检测热点的快速方法。在本发明的一些实施例中，定位敏感点。使用光刻模型来模拟敏感点附近的几何形状，以产生敏感点周围区域的模型。使用诸如强度（光）或基于对比度的评分来测量敏感点。

6. 发明授权

US07707526B2 Predicting IC manufacturing yield based on hotspots 有权
标题翻译：基于热点预测IC制造产量
公开(公告)号：US07707526B2
公开(公告)日：2010-04-27
申请号：US11805916
申请日：2007-05-25
申请人： Qing Su , Charles C. Chiang
发明人： Qing Su , Charles C. Chiang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： One embodiment of the present invention provides a system that predicts a manufacturing yield of a chip. During operation, the system first receives a chip layout. Next, the system identifies hotspots within the chip layout, wherein a hotspot is a location within the chip layout wherein a yield-indicative variable value falls in a low manufacturable range. The system then obtains yield scores for the hotspots, wherein a yield score indicates a failure probability for a corresponding hotspot. Next, the system predicts the manufacturing yield for the chip based on the hotspots and the yield scores for the hotspots.
摘要翻译：本发明的一个实施例提供一种预测芯片的制造成品率的系统。在操作过程中，系统首先接收芯片布局。接下来，系统识别芯片布局内的热点，其中热点是芯片布局内的位置，其中屈服指示变量值落在低可制造范围内。然后，系统获得热点的产出分数，其中收益率分数指示相应热点的失败概率。接下来，该系统基于热点估计芯片的制造成品率以及热点的成品率。

7. 发明申请

US20090187876A1 STEINER TREE BASED APPROACH FOR POLYGON FRACTURING 有权
标题翻译：基于STENER TREE的多边形破碎方法
公开(公告)号：US20090187876A1
公开(公告)日：2009-07-23
申请号：US12017025
申请日：2008-01-19
申请人： Qing Su , Yongqiang Lu , Charles C. Chiang
发明人： Qing Su , Yongqiang Lu , Charles C. Chiang
IPC分类号： G06F17/50
CPC分类号： G03F1/68
摘要： Roughly described, a method for mask data preparation is described, for use with a preliminary mask layout that includes a starting polygon, the vertices of the starting polygon including I-points (vertices of the starting polygon having an interior angle greater than 90 degrees), including steps of developing a rectilinear partition tree on at least the I-points of the starting polygon, and using the edges of the partition tree to define the partition of the starting polygon into sub-polygons for mask writing.
摘要翻译：粗略地描述了一种用于掩模数据准备的方法，用于包括起始多边形的初步掩模布局，起始多边形的顶点包括I点（具有大于90度的内角的起始多边形的顶点）包括在至少起始多边形的I点上开发直线分区树的步骤，以及使用分区树的边将起始多边形的分区定义为用于掩码写入的子多边形。

8. 发明授权

US07543255B2 Method and apparatus to reduce random yield loss 有权
标题翻译：减少随机产量损失的方法和装置
公开(公告)号：US07543255B2
公开(公告)日：2009-06-02
申请号：US11725007
申请日：2007-03-16
申请人： Subarnarekha Sinha , Qing Su , Charles C. Chiang
发明人： Subarnarekha Sinha , Qing Su , Charles C. Chiang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： One embodiment of the present invention provides a system that reduces random yield loss. During operation, the system can receive a design layout. The system may also receive weighting factors that are associated with the particle densities in the metal regions and the empty regions. Next, the system can determine local critical-area-ratios and optimization potentials for a set of wire-segments. The system can then select a wire segment, and compare its local critical-area-ratio with a global critical-area-ratio. Next, the system can use the result of the comparison to determine a layout optimization. The system can then apply the layout optimization to the wire segment to obtain an improved layout.
摘要翻译：本发明的一个实施方案提供了减少随机产率损失的系统。在操作过程中，系统可以接收设计布局。系统还可以接收与金属区域和空区域中的颗粒密度相关联的加权因子。接下来，系统可以确定一组线段的局部临界面积比和优化电位。然后，系统可以选择一个线段，并将其局部临界面积比与全局临界面积比进行比较。接下来，系统可以使用比较结果来确定布局优化。然后，系统可以将布局优化应用于线段以获得改进的布局。

9. 发明授权

US07496883B2 Method and apparatus for identifying and correcting phase conflicts 有权
标题翻译：用于识别和纠正相位冲突的方法和装置
公开(公告)号：US07496883B2
公开(公告)日：2009-02-24
申请号：US11127694
申请日：2005-05-11
申请人： Subarnarekha Sinha , Charles C. Chiang
发明人： Subarnarekha Sinha , Charles C. Chiang
IPC分类号： G06F17/50
CPC分类号： G03F1/30
摘要： One embodiment of the present invention provides a system that identifies a substantially minimal set of phase conflicts in a PSM-layout that when corrected renders the layout phase-assignable. During operation, the system constructs a phase-conflict graph from a PSM-layout such that the PSM-layout is phase-assignable if and only if the phase-conflict graph is bipartite. Next, the system removes a first set of edges from the phase-conflict graph to make the graph planar, and then removes a second set of edges to make the graph bipartite. The system then adds zero or more edges of the first set of edges, and determines a set of phase conflicts in the PSM-layout based on the remaining edges in the first set of edges and the second set of edges. The system can also be used to correct a given set of phase conflicts in a PSM-layout.
摘要翻译：本发明的一个实施例提供了一种系统，其识别PSM布局中的基本上最小的相位冲突集合，其在被校正时呈现布局相位可分配。在操作期间，系统从PSM布局构建相冲突图，使得当且仅当相冲突图是二分的时候，PSM布局是可相位分配的。接下来，系统从相冲突图中移除第一组边，使图形平面，然后移除第二组边，使图形成二分。然后，系统添加第一组边缘的零个或多个边缘，并且基于第一组边缘和第二组边缘中的剩余边缘来确定PSM布局中的一组相位冲突。该系统还可用于纠正PSM布局中给定的一组相位冲突。

10. 发明申请

US20080301623A1 Lithography Suspect Spot Location and Scoring System 有权
标题翻译：光刻可疑点位置和评分系统
公开(公告)号：US20080301623A1
公开(公告)日：2008-12-04
申请号：US11756596
申请日：2007-05-31
申请人： Min-Chun Tsai , Charles C. Chiang
发明人： Min-Chun Tsai , Charles C. Chiang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A fast method to detect hot spots using foundry independent models that do not require RET/OPC synthesis is presented. In some embodiments of the present invention, sensitive spots are located. Lithography models are used to simulate the geometry near the sensitive spots to produce a model of the area around the sensitive spots. The sensitive spots are scored using a measure such as intensity (of light) or scoring based on contrast.
摘要翻译：提出了一种使用不需要RET / OPC合成的代工独立模型来检测热点的快速方法。在本发明的一些实施例中，定位敏感点。使用光刻模型来模拟敏感点附近的几何形状，以产生敏感点周围区域的模型。使用诸如强度（光）或基于对比度的评分来测量敏感点。

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