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1. 发明申请

US20160148947A1 MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
标题翻译：记忆装置及其制造方法
公开(公告)号：US20160148947A1
公开(公告)日：2016-05-26
申请号：US14845541
申请日：2015-09-04
申请人： Jun-Ho SEO , Daewoong KANG , Hyoje BANG , Changsub LEE , Sunghoi HUR
发明人： Jun-Ho SEO , Daewoong KANG , Hyoje BANG , Changsub LEE , Sunghoi HUR
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L27/11565
摘要： A memory device includes a stack including gate electrodes vertically stacked on a substrate and having a vertical hole, an active pillar disposed in the vertical hole and providing a vertical channel, a charge storage section interposed between the active pillar and the gate electrodes, a blocking dielectric interposed between the charge storage section and the gate electrodes, a tunnel dielectric interposed between the charge storage section and the active pillar, insulation filling an inner hole of the active pillar, and a fixed charge layer interposed between the filling insulation and the active pillar. Measures are taken to address phenomena in which current would otherwise be adversely affected near an interface between the vertical channel and the filling insulation.
摘要翻译：存储器件包括：堆叠，其包括垂直堆叠在基板上并具有垂直孔的栅电极，设置在垂直孔中的主动柱并提供垂直沟道;夹在有源柱和栅电极之间的电荷存储部，介于电荷存储部和栅电极之间的电介质，介于电荷存储部和有源支柱之间的隧道电介质，填充有源支柱的内孔的绝缘填充物和插入填充绝缘体和有源支柱之间的固定电荷层。采取措施来解决在垂直通道和填充绝缘体之间的界面附近电流将受到不利影响的现象。

2. 发明申请

US20160118126A1 NONVOLATILE MEMORY DEVICES AND PROGRAM METHOD THEREOF 审中-公开
标题翻译：非易失性存储器件及其程序方法
公开(公告)号：US20160118126A1
公开(公告)日：2016-04-28
申请号：US14854097
申请日：2015-09-15
申请人： Sungsu Moon , Changsub LEE , Raeyoung LEE , Soyeong GWAK
发明人： Sungsu Moon , Changsub LEE , Raeyoung LEE , Soyeong GWAK
IPC分类号： G11C16/12 , G11C16/34 , G06F12/02
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/10 , G11C16/3459 , G11C2211/5621
摘要： A program method of a nonvolatile memory device is provided which includes programming memory cells to a target state using a verification voltage and an incremental step pulse, selecting memory cells, each having a threshold voltage lower than a supplementary verification voltage, from among the memory cells programmed to the target state, and applying a supplementary program voltage to the selected memory cells. The supplementary verification voltage is equal to or higher than the verification voltage, and the supplementary program voltage is equal to or lower than a program voltage provided in a program loop where a programming of the memory cells to the target state is completed.
摘要翻译：提供了一种非易失性存储器件的编程方法，其包括使用验证电压和增量步进脉冲将存储器单元编程为目标状态，从存储单元中选择各自具有低于辅助验证电压的阈值电压的存储单元被编程到目标状态，并将补充编程电压施加到所选存储单元。辅助验证电压等于或高于验证电压，并且补充编程电压等于或低于在编程到目标状态的存储器单元的程序循环中提供的编程电压。

3. 发明授权

US09165660B2 Non-volatile memory devices and related operating methods 有权
标题翻译：非易失性存储器件及相关操作方法
公开(公告)号：US09165660B2
公开(公告)日：2015-10-20
申请号：US14471231
申请日：2014-08-28
申请人： Dong-Jun Lee , Sungsu Moon , Jaihyuk Song , Changsub Lee
发明人： Dong-Jun Lee , Sungsu Moon , Jaihyuk Song , Changsub Lee
IPC分类号： G11C16/04 , G11C16/10 , G11C16/26
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/26 , G11C16/3427
摘要： Non-volatile memory devices and related methods are provided. The non-volatile memory devices include a memory cell array having a plurality of cell strings, each cell string including: a plurality of memory cells stacked in a direction perpendicular to a substrate, a ground selection transistor between the plurality of memory cells and the substrate, and a string selection transistor between the plurality of memory cells and a bit line; an address decoder coupled to the plurality of memory cells in the plurality of cell strings through word lines, to the string selection transistors in the plurality of cell strings through string selection lines, and to the ground selection transistors in the plurality of cell strings through a ground selection line; a read/write circuit coupled to the string selection transistors in the plurality of cell strings through the bit lines; and control logic configured to adjust a substrate voltage applied to the substrate such that threshold voltages of the ground selection transistors are higher than a predetermined level during read operations for at least one of the plurality of memory cells in the plurality of cell strings.
摘要翻译：提供了非易失性存储器件和相关方法。非易失性存储器件包括具有多个单元串的存储单元阵列，每个单元串包括：沿垂直于衬底的方向堆叠的多个存储单元，多个存储单元之间的接地选择晶体管和衬底和多个存储单元之间的串选择晶体管和位线; 通过字线将多个单元串中的多个存储单元耦合到地址解码器，通过串选择线连接到多个单元串中的串选择晶体管，以及通过一个单元串的多个单元串中的地选择晶体管地面选线; 读/写电路，通过位线耦合到多个单元串中的串选择晶体管; 以及控制逻辑，被配置为调整施加到所述衬底的衬底电压，使得所述接地选择晶体管的阈值电压在所述多个单元串中的所述多个存储器单元中的至少一个的读操作期间高于预定电平。

4. 发明申请

US20160351582A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20160351582A1
公开(公告)日：2016-12-01
申请号：US15165135
申请日：2016-05-26
申请人： Nambin Kim , DAEWOONG KANG , DAE SIN KIM , KWANG SOO SEOL , HOMIN SON , CHANGSUB LEE , SEUNGHYUN LIM , SUNGHOI HUR
发明人： Nambin Kim , DAEWOONG KANG , DAE SIN KIM , KWANG SOO SEOL , HOMIN SON , CHANGSUB LEE , SEUNGHYUN LIM , SUNGHOI HUR
IPC分类号： H01L27/115 , H01L29/792
CPC分类号： H01L27/11582 , H01L27/1157
摘要： Provided is a semiconductor device including a substrate, gate electrodes vertically stacked on the substrate, insulating patterns between the gate electrodes, an active pillar provided to penetrate the gate electrodes and the insulating patterns and electrically coupled with the substrate, and a memory pattern provided between the gate electrodes and the active pillar and between the insulating patterns and the active pillar. The gate electrodes include edge portions extending between the memory pattern and the insulating patterns.
摘要翻译：本发明提供一种半导体器件，包括基板，垂直堆叠在基板上的栅电极，栅电极之间的绝缘图案，设置成穿过栅电极的活性柱和绝缘图案，并与基板电耦合，以及存储图案，栅电极和有源支柱以及绝缘图案和有源支柱之间。栅电极包括在存储器图案和绝缘图案之间延伸的边缘部分。

5. 发明申请

US20150063037A1 Non-Volatile Memory Devices and Related Operating Methods 有权
标题翻译：非易失性存储器件及相关操作方法
公开(公告)号：US20150063037A1
公开(公告)日：2015-03-05
申请号：US14471231
申请日：2014-08-28
申请人： Dong-Jun Lee , Sungsu Moon , Jaihyuk Song , Changsub Lee
发明人： Dong-Jun Lee , Sungsu Moon , Jaihyuk Song , Changsub Lee
IPC分类号： G11C16/10 , G11C16/26 , G11C16/04
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/26 , G11C16/3427
摘要： Non-volatile memory devices and related methods are provided. The non-volatile memory devices include a memory cell array having a plurality of cell strings, each cell string including: a plurality of memory cells stacked in a direction perpendicular to a substrate, a ground selection transistor between the plurality of memory cells and the substrate, and a string selection transistor between the plurality of memory cells and a bit line; an address decoder coupled to the plurality of memory cells in the plurality of cell strings through word lines, to the string selection transistors in the plurality of cell strings through string selection lines, and to the ground selection transistors in the plurality of cell strings through a ground selection line; a read/write circuit coupled to the string selection transistors in the plurality of cell strings through the bit lines; and control logic configured to adjust a substrate voltage applied to the substrate such that threshold voltages of the ground selection transistors are higher than a predetermined level during read operations for at least one of the plurality of memory cells in the plurality of cell strings.
摘要翻译：提供了非易失性存储器件和相关方法。非易失性存储器件包括具有多个单元串的存储单元阵列，每个单元串包括：沿垂直于衬底的方向堆叠的多个存储单元，多个存储单元之间的接地选择晶体管和衬底和多个存储单元之间的串选择晶体管和位线; 通过字线将多个单元串中的多个存储单元耦合到地址解码器，通过串选择线连接到多个单元串中的串选择晶体管，以及通过一个单元串的多个单元串中的地选择晶体管地面选线; 读/写电路，通过位线耦合到多个单元串中的串选择晶体管; 以及控制逻辑，被配置为调整施加到所述衬底的衬底电压，使得所述接地选择晶体管的阈值电压在所述多个单元串中的所述多个存储器单元中的至少一个的读操作期间高于预定电平。

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