专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060292883A1 ETCHING OF SILICON NITRIDE WITH IMPROVED NITRIDE-TO-OXIDE SELECTIVITY UTILIZING HALOGEN BROMIDE/CHLORINE PLASMA 审中-公开
标题翻译：利用改良的卤化物/氯等离子体改善氮氧化物选择性的硅氮化物的蚀刻
公开(公告)号：US20060292883A1
公开(公告)日：2006-12-28
申请号：US11160521
申请日：2005-06-28
申请人： Chang-Hu Tsai
发明人： Chang-Hu Tsai
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/31144 , H01L21/76802 , H01L21/76811 , H01L29/6656
摘要： A method of manufacturing a semiconductor device is disclosed. A gate is formed on a semiconductor substrate. A gate oxide is formed between the gate and the semiconductor substrate. A silicon oxide liner layer is deposited on the gate and on the semiconductor substrate. A silicon nitride layer is then deposited on the silicon oxide liner layer. The silicon nitride layer is anisotropically etched by employing plasma created by using plasma source gas containing hydrogen bromide and chlorine thereby forming spacer on sidewalls of the gate. The hydrogen bromide plasma is produced at a temperature of about 50-150° C., a pressure of 5-200 mTorr, a source power of no less than 800 Watts, and a bias power of about 100-200 Watts.
摘要翻译：公开了制造半导体器件的方法。在半导体衬底上形成栅极。在栅极和半导体衬底之间形成栅极氧化物。氧化硅衬层沉积在栅极和半导体衬底上。然后在氧化硅衬垫层上沉积氮化硅层。通过使用通过使用含有溴化氢和氯的等离子体源气体产生的等离子体来对氮化硅层进行各向异性蚀刻，从而在栅极的侧壁上形成间隔物。溴化氢等离子体在约50-150℃的温度，5-200mTorr的压力，不低于800瓦的光源功率和约100-200瓦的偏压功率下产生。

2. 发明申请

US20070051696A1 METHOD FOR REDUCING CRITICAL DIMENSION AND SEMICONDUCTOR ETCHING METHOD 有权
标题翻译：减少关键尺寸和半导体蚀刻方法的方法
公开(公告)号：US20070051696A1
公开(公告)日：2007-03-08
申请号：US11161996
申请日：2005-08-25
申请人： Chang-Hu Tsai
发明人： Chang-Hu Tsai
IPC分类号： C23F1/00 , H01L21/461 , B44C1/22
CPC分类号： H01L21/31144 , H01L21/3088 , H01L21/31116 , H01L21/32139
摘要： A method of reducing critical dimension is provided. A dielectric layer is formed on a substrate. Then, a patterned photoresist is formed on the dielectric layer to expose part of the dielectric layer, wherein the patterned photoresist has a first line width. An etching process is performed to remove the exposed dielectric layer by using the patterned photoresist as an etching mask, wherein the final line width of the dielectric layer is smaller than the first line width. The conditions of the etching process include an etching pressure at 80 torr to 400 torr, an etching gas that includes a fluorocarbon compound and oxygen, wherein the ratio of the fluorocarbon compound to the oxygen is large than 0 and less than 10. Consequently, the etching process can be stabilized to form a smooth sidewall for the gate and to provide a uniform critical dimension.
摘要翻译：提供了一种降低临界尺寸的方法。在基板上形成电介质层。然后，在电介质层上形成图案化的光致抗蚀剂以暴露电介质层的一部分，其中图案化的光致抗蚀剂具有第一线宽度。通过使用图案化的光致抗蚀剂作为蚀刻掩模来执行蚀刻工艺以去除暴露的电介质层，其中电介质层的最终线宽小于第一线宽度。蚀刻工艺的条件包括80托至400托的蚀刻压力，包括碳氟化合物和氧的蚀刻气体，其中碳氟化合物与氧的比例大于0且小于10.因此，蚀刻过程可以被稳定以形成用于栅极的平滑侧壁并提供均匀的临界尺寸。

3. 发明授权

US07268086B2 Method for reducing critical dimension and semiconductor etching method 有权
标题翻译：降低临界尺寸和半导体蚀刻方法的方法
公开(公告)号：US07268086B2
公开(公告)日：2007-09-11
申请号：US11161996
申请日：2005-08-25
申请人： Chang-Hu Tsai
发明人： Chang-Hu Tsai
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/3088 , H01L21/31116 , H01L21/32139
摘要： A method of reducing critical dimension is provided. A dielectric layer is formed on a substrate. Then, a patterned photoresist is formed on the dielectric layer to expose part of the dielectric layer, wherein the patterned photoresist has a first line width. An etching process is performed to remove the exposed dielectric layer by using the patterned photoresist as an etching mask, wherein the final line width of the dielectric layer is smaller than the first line width. The conditions of the etching process include an etching pressure at 80 torr to 400 torr, an etching gas that includes a fluorocarbon compound and oxygen, wherein the ratio of the fluorocarbon compound to the oxygen is large than 0 and less than 10. Consequently, the etching process can be stabilized to form a smooth sidewall for the gate and to provide a uniform critical dimension.
摘要翻译：提供了一种降低临界尺寸的方法。在基板上形成电介质层。然后，在电介质层上形成图案化的光致抗蚀剂以暴露电介质层的一部分，其中图案化的光致抗蚀剂具有第一线宽度。通过使用图案化的光致抗蚀剂作为蚀刻掩模来执行蚀刻工艺以去除暴露的电介质层，其中电介质层的最终线宽小于第一线宽度。蚀刻工艺的条件包括80托至400托的蚀刻压力，包括碳氟化合物和氧的蚀刻气体，其中碳氟化合物与氧的比例大于0且小于10.因此，蚀刻过程可以被稳定以形成用于栅极的平滑侧壁并提供均匀的临界尺寸。

4. 发明申请

US20060068593A1 PATTERNING METHOD 审中-公开
标题翻译：绘图方法
公开(公告)号：US20060068593A1
公开(公告)日：2006-03-30
申请号：US10711678
申请日：2004-09-30
申请人： Chang-Hu Tsai , Prudence Wu
发明人： Chang-Hu Tsai , Prudence Wu
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/3065 , H01L21/31116 , H01L21/32137
摘要： A patterning method is provided. First, a substrate comprising a film formed thereon is provided. Then, a photoresist layer is formed over the film. Next, the photoresist layer is developed to form a patterned photoresist layer. Then, the film is etched using a dry etching method. In addition, the dry etching method is performed at a temperature range of about −50° C. to about 50° C. using the patterned photoresist layer as an etching mask.
摘要翻译：提供了图案化方法。首先，提供包含其上形成的膜的基板。然后，在膜上形成光致抗蚀剂层。接下来，将光致抗蚀剂层显影以形成图案化的光致抗蚀剂层。然后，使用干蚀刻方法蚀刻该膜。此外，使用图案化的光致抗蚀剂层作为蚀刻掩模，在约-50℃至约50℃的温度范围内进行干蚀刻方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式