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1. 发明授权

US08558359B2 Semiconductor package having lead frames 失效
标题翻译：具有引线框架的半导体封装
公开(公告)号：US08558359B2
公开(公告)日：2013-10-15
申请号：US13352146
申请日：2012-01-17
申请人： Chang Hyun Lim , Chang Jae Heo , Young Ki Lee , Sung Keun Park
发明人： Chang Hyun Lim , Chang Jae Heo , Young Ki Lee , Sung Keun Park
IPC分类号： H01L23/495 , H01L23/48 , H01L23/52
CPC分类号： H01L23/36 , H01L23/49531 , H01L23/49537 , H01L23/49811 , H01L2224/48091 , H01L2924/1305 , H01L2924/13055 , H01L2924/00 , H01L2924/00014
摘要： Disclosed herein is a semiconductor package, including: a substrate having a first surface and a second surface; at least one semiconductor device formed on the first surface of the substrate; first lead frames respectively formed at both sides of the first surface of the substrate; and second lead frames respectively formed at both sides of the second surface of the substrate, wherein the first lead frame and the second lead frame are spaced apart from each other by an isolation distance base.
摘要翻译：本文公开了一种半导体封装，包括：具有第一表面和第二表面的基板; 形成在所述基板的第一表面上的至少一个半导体器件; 分别形成在基板的第一表面的两侧的第一引线框架; 以及分别形成在所述基板的第二表面的两侧的第二引线框架，其中所述第一引线框架和所述第二引线框架通过隔离距离基座间隔开。

2. 发明申请

US20130105954A1 SEMICONDUCTOR PACKAGE 失效
标题翻译：半导体封装
公开(公告)号：US20130105954A1
公开(公告)日：2013-05-02
申请号：US13352146
申请日：2012-01-17
申请人： Chang Hyun Lim , Chang Jae Heo , Young Ki Lee , Sung Keun Park
发明人： Chang Hyun Lim , Chang Jae Heo , Young Ki Lee , Sung Keun Park
IPC分类号： H01L23/495
CPC分类号： H01L23/36 , H01L23/49531 , H01L23/49537 , H01L23/49811 , H01L2224/48091 , H01L2924/1305 , H01L2924/13055 , H01L2924/00 , H01L2924/00014
摘要： Disclosed herein is a semiconductor package, including: a substrate having a first surface and a second surface; at least one semiconductor device formed on the first surface of the substrate; first lead frames respectively formed at both sides of the first surface of the substrate; and second lead frames respectively formed at both sides of the second surface of the substrate, wherein the first lead frame and the second lead frame are spaced apart from each other by an isolation distance base.
摘要翻译：本文公开了一种半导体封装，包括：具有第一表面和第二表面的基板; 形成在所述基板的第一表面上的至少一个半导体器件; 分别形成在基板的第一表面的两侧的第一引线框架; 以及分别形成在所述基板的第二表面的两侧的第二引线框架，其中所述第一引线框架和所述第二引线框架通过隔离距离基座间隔开。

3. 发明申请

US20130033297A1 SEMICONDUCTOR CIRCUIT 有权
标题翻译：半导体电路
公开(公告)号：US20130033297A1
公开(公告)日：2013-02-07
申请号：US13532645
申请日：2012-06-25
申请人： Chang Jae Heo
发明人： Chang Jae Heo
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K5/1252
摘要： The present invention relates to a semiconductor circuit including: a delay unit for delaying an input signal by a predetermined time to output the delayed signal; a voltage adjusting unit for charging and discharging voltage according to a level of the input signal; and a combination unit for controlling the charging and discharging operations of the voltage adjusting unit according to signals generated using the level of the input signal and a level of the signal output from the delay unit, and it is possible to effectively remove low level noise and high level noise which are respectively mixed in a high level signal and a low level signal input to the semiconductor circuit.
摘要翻译：本发明涉及一种半导体电路，包括：延迟单元，用于将输入信号延迟预定时间以输出延迟信号; 电压调节单元，用于根据输入信号的电平对电压进行充放电; 以及组合单元，用于根据使用输入信号的电平和从延迟单元输出的信号的电平产生的信号来控制电压调节单元的充电和放电操作，并且可以有效地去除低电平噪声和高电平噪声分别混合在输入到半导体电路的高电平信号和低电平信号中。

4. 发明授权

US08674740B2 Noise removing delay circuit 有权
标题翻译：去噪延迟电路
公开(公告)号：US08674740B2
公开(公告)日：2014-03-18
申请号：US13532645
申请日：2012-06-25
申请人： Chang Jae Heo
发明人： Chang Jae Heo
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K5/1252
摘要： The present invention relates to a semiconductor circuit including: a delay unit for delaying an input signal by a predetermined time to output the delayed signal; a voltage adjusting unit for charging and discharging voltage according to a level of the input signal; and a combination unit for controlling the charging and discharging operations of the voltage adjusting unit according to signals generated using the level of the input signal and a level of the signal output from the delay unit, and it is possible to effectively remove low level noise and high level noise which are respectively mixed in a high level signal and a low level signal input to the semiconductor circuit.
摘要翻译：本发明涉及一种半导体电路，包括：延迟单元，用于将输入信号延迟预定时间以输出延迟信号; 电压调节单元，用于根据输入信号的电平对电压进行充放电; 以及组合单元，用于根据使用输入信号的电平和从延迟单元输出的信号的电平产生的信号来控制电压调节单元的充电和放电操作，并且可以有效地去除低电平噪声和高电平噪声分别混合在输入到半导体电路的高电平信号和低电平信号中。

5. 发明申请

US20130038356A1 OUTPUT DRIVING CIRCUIT AND TRANSISTOR OUTPUT CIRCUIT 有权
标题翻译：输出驱动电路和晶体管输出电路
公开(公告)号：US20130038356A1
公开(公告)日：2013-02-14
申请号：US13569094
申请日：2012-08-07
申请人： Chang Jae Heo
发明人： Chang Jae Heo
IPC分类号： H03K3/00
CPC分类号： H03K17/08122 , H03K3/356104
摘要： Disclosed herein are an output driving circuit and a transistor output circuit. The output driving circuit includes: a reference voltage generating unit generating a reference voltage; a level shift unit including a transistor latch and turning off a first transistor of a driving circuit or driving the first transistor; a driving circuit unit including the first transistor that is driven to apply power to a gate of an output transistor and a second transistor that is driven complementarily to the first transistor to lower a gate voltage of the output transistor and drive the output transistor; and an withstand voltage protecting unit that is driven by receiving a reference voltage and includes a first withstand voltage protecting unit for protecting transistors of the transistor latch and the first transistor for stable operations thereof and a second withstand voltage protecting unit for protecting the output transistor for a stable operation thereof.
摘要翻译：这里公开了输出驱动电路和晶体管输出电路。输出驱动电路包括：产生参考电压的参考电压产生单元; 电平移位单元，包括晶体管锁存器，并且关断驱动电路的第一晶体管或驱动第一晶体管; 驱动电路单元，包括被驱动以对输出晶体管的栅极施加功率的第一晶体管和与第一晶体管互补驱动的第二晶体管，以降低输出晶体管的栅极电压并驱动输出晶体管; 以及耐受电压保护单元，其通过接收参考电压而被驱动并且包括用于保护晶体管锁存器和第一晶体管的晶体管的第一耐受电压保护单元，用于其稳定操作;以及第二耐受电压保护单元，用于保护输出晶体管其稳定的操作。

6. 发明申请

US20130038355A1 OUTPUT DRIVING CIRCUIT AND TRANSISTOR OUTPUT CIRCUIT 审中-公开
标题翻译：输出驱动电路和晶体管输出电路
公开(公告)号：US20130038355A1
公开(公告)日：2013-02-14
申请号：US13415735
申请日：2012-03-08
申请人： Chang Jae HEO
发明人： Chang Jae HEO
IPC分类号： H03K3/00
CPC分类号： H03K17/164
摘要： The present invention relates to an output driving circuit and a transistor output circuit. In accordance with an embodiment of the present invention, an output driving circuit including: a first driving circuit unit driven according to on operation of a first switch to supply high voltage power source to a gate of an output transistor; a second driving circuit unit driven by a one-shot pulse generated according to on operation of a second switch, which operates complementarily with the first switch, to discharge a gate-source capacitance of the output transistor; and an output driving voltage clamping unit disposed between a high voltage power source terminal and the gate of the output transistor in parallel with the first driving circuit unit to maintain a gate potential of the output transistor discharged according to the on operation of the second switch is provided.
摘要翻译：本发明涉及输出驱动电路和晶体管输出电路。根据本发明的实施例，一种输出驱动电路，包括：第一驱动电路单元，根据第一开关的操作驱动，向输出晶体管的栅极提供高压电源; 由与第一开关互补操作的第二开关的操作产生的单触发脉冲驱动的第二驱动电路单元，以对输出晶体管的栅极 - 源极电容进行放电; 以及输出驱动电压钳位单元，其设置在与第一驱动电路单元并联的高压电源端子和输出晶体管的栅极之间，以维持根据第二开关的接通操作而放电的输出晶体管的栅极电位提供。

7. 发明授权

US08823425B2 Output driving circuit and transistor output circuit 有权
标题翻译：输出驱动电路和晶体管输出电路
公开(公告)号：US08823425B2
公开(公告)日：2014-09-02
申请号：US13569094
申请日：2012-08-07
申请人： Chang Jae Heo
发明人： Chang Jae Heo
IPC分类号： H03B1/00
CPC分类号： H03K17/08122 , H03K3/356104
摘要： Disclosed herein are an output driving circuit and a transistor output circuit. The output driving circuit includes: a reference voltage generating unit generating a reference voltage; a level shift unit including a transistor latch and turning off a first transistor of a driving circuit or driving the first transistor; a driving circuit unit including the first transistor that is driven to apply power to a gate of an output transistor and a second transistor that is driven complementarily to the first transistor to lower a gate voltage of the output transistor and drive the output transistor; and an withstand voltage protecting unit that is driven by receiving a reference voltage and includes a first withstand voltage protecting unit for protecting transistors of the transistor latch and the first transistor for stable operations thereof and a second withstand voltage protecting unit for protecting the output transistor for a stable operation thereof.
摘要翻译：这里公开了输出驱动电路和晶体管输出电路。输出驱动电路包括：产生参考电压的参考电压产生单元; 电平移位单元，包括晶体管锁存器，并且关断驱动电路的第一晶体管或驱动第一晶体管; 驱动电路单元，包括被驱动以对输出晶体管的栅极施加功率的第一晶体管和与第一晶体管互补驱动的第二晶体管，以降低输出晶体管的栅极电压并驱动输出晶体管; 以及耐受电压保护单元，其通过接收参考电压而被驱动，并且包括用于保护晶体管锁存器和第一晶体管的晶体管的第一耐受电压保护单元以用于其稳定操作;以及第二耐受电压保护单元，用于保护输出晶体管其稳定的操作。

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