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1. 发明专利

DE202014001739U1 Planarteilbasierter Spielzeugbausatz 未知
公开(公告)号：DE202014001739U1
公开(公告)日：2014-03-28
申请号：DE202014001739
申请日：2014-02-18
申请人： CHANG CHUN YEH , HUNG CHIA WEN
IPC分类号： A63H33/08
摘要： Planarteilbasierter Spielzeugbausatz, umfassend mehrere planare Teile, die unterschiedliche Formen aufweisen und durch Stanzen einer Planarmaterialplatte mithilfe einer Stanzmaschine hergestellt sind, wobei die planare Teile Folgendes einschließen: wenigstens ein Körperteil mit wenigstens einem geschlitzten Ring, der an einer Außenseite mit einem Schneideschlitz versehen ist und eine kreisförmige Umschließung mit einem schmalen Abschnitt und einem breiten Abschnitt aufweist; und wenigstens ein Gliedmaßenteil mit wenigstens einem geschlossene Ring oder wenigstens einem geschlitzten Ring, wobei der geschlossene Ring einen Durchmesser aufweist, der größer als eine Breite des schmalen Abschnitts des geschlitzten Rings und kleiner als eine Breite des breiten Abschnitts des geschlitzte Rings ist, wobei der geschlossene Ring jedes Gliedmaßenteils dazu konfiguriert ist, durch den Schneideschlitz an der Außenseite des geschlitzten Rings des Körperteils zu treten und um den schmalen Abschnitt oder den breiten Abschnitt des geschlitzten Rings herum angbracht zu werden, um das Gliedmaßenteil und das Körperteil aneinander zu koppeln, und außerdem dazu konfiguriert ist, dass der geschlossene Ring durch den Schneideschlitz an der Außenseite des geschlitzten Rings eines anderen Gliedmaßenteilschlitzes tritt, um um den schmalen Abschnitt oder den breiten Abschnitt des geschlitzte Ring herum angebracht zu werden und die zwei Gliedmaßenteile aneinander zu koppeln, wobei, wenn der geschlossene Ring des Gliedmaßenteils um den schmalen Abschnitt des geschlitzten Rings herum angebracht ist, das Gliedmaßenteil schwingen kann, und wenn der geschlossene Ring des Gliedmaßenteils um den breiten Abschnitt des geschlitzten Rings herum angebracht ist, das Gliedmaßenteil in einem bestimmten Winkel fixiert ist, der von einem Spielenden einstellbar ist.

2. 发明申请

US20120083055A1 STRUCTURE AND METHOD FOR DETERMINING A DEFECT IN INTEGRATED CIRCUIT MANUFACTURING PROCESS 审中-公开
标题翻译：用于确定集成电路制造过程中的缺陷的结构和方法
公开(公告)号：US20120083055A1
公开(公告)日：2012-04-05
申请号：US13323634
申请日：2011-12-12
申请人： Hong XIAO , Jack Y. JAU , Chang Chun YEH
发明人： Hong XIAO , Jack Y. JAU , Chang Chun YEH
IPC分类号： H01L21/66
CPC分类号： H01L22/12 , H01L22/24
摘要： The present invention discloses a structure and method for determining a defect in integrated circuit manufacturing process, wherein the structure comprises a plurality of normal active areas formed in a plurality of first arrays and a plurality of defective active areas formed in a plurality of second arrays. The first arrays and second arrays are interlaced, and the defect is determined by monitoring a voltage contrast from a charged particle microscope image of the active areas.
摘要翻译：本发明公开了一种用于确定集成电路制造过程中的缺陷的结构和方法，其中该结构包括形成在多个第一阵列中的多个正常有源区和形成在多个第二阵列中的多个有缺陷的有源区。第一阵列和第二阵列是交错的，并且通过监视来自有源区域的带电粒子显微镜图像的电压对比来确定缺陷。

3. 发明授权

US08089297B2 Structure and method for determining a defect in integrated circuit manufacturing process 有权
标题翻译：用于确定集成电路制造过程中的缺陷的结构和方法
公开(公告)号：US08089297B2
公开(公告)日：2012-01-03
申请号：US12110147
申请日：2008-04-25
申请人： Hong Xiao , Jack Jau , Chang Chun Yeh
发明人： Hong Xiao , Jack Jau , Chang Chun Yeh
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： H01L22/12 , H01L22/24
摘要： The present invention discloses a structure and method for determining a defect in integrated circuit manufacturing process, wherein the structure comprises a plurality of normal active areas formed in a plurality of first arrays and a plurality of defective active areas formed in a plurality of second arrays. The first arrays and second arrays are interlaced, and the defect is determined by monitoring a voltage contrast from a charged particle microscope image of the active areas.
摘要翻译：本发明公开了一种用于确定集成电路制造过程中的缺陷的结构和方法，其中该结构包括形成在多个第一阵列中的多个正常有源区和形成在多个第二阵列中的多个有缺陷的有源区。第一阵列和第二阵列是交错的，并且通过监视来自有源区域的带电粒子显微镜图像的电压对比来确定缺陷。

4. 发明授权

US08063363B2 Method and apparatus for charged particle beam inspection 有权
标题翻译：带电粒子束检查的方法和装置
公开(公告)号：US08063363B2
公开(公告)日：2011-11-22
申请号：US12400757
申请日：2009-03-09
申请人： Chang Chun Yeh , Shih-Tsuan Chang
发明人： Chang Chun Yeh , Shih-Tsuan Chang
IPC分类号： G01N23/00
CPC分类号： H01J37/28 , H01J37/20 , H01J37/265 , H01J2237/20228 , H01J2237/2817
摘要： A method, apparatus and computer readable medium for charged particle beam inspection of a sample comprising at least one sampling region and at least one skip region is disclosed. The method, apparatus and computer readable medium comprise receiving an imaging recipe which at least comprises information of the area of the sampling and skip regions; calculating a default stage speed according to the imaging recipe; calculating an alternative stage speed at least according to the default stage speed, the sampling region area information, and the skip region area information; calculating at least one imaging scan compensation offset at least according to the alternative stage speed; and inspecting the sample at the alternative stage speed while adjusting the motion of the charged particle beam according to the imaging scan compensation offsets, such that the charged particle beam tightly follows the motion of the stage and images only the sampling regions on the sample.
摘要翻译：公开了一种用于对包含至少一个采样区域和至少一个跳过区域的样本进行带电粒子束检查的方法，设备和计算机可读介质。该方法，装置和计算机可读介质包括接收至少包括采样和跳过区域的区域的信息的成像配方; 根据成像配方计算默认舞台速度; 至少根据默认级速度，采样区域信息和跳过区域区域信息计算替代级速度; 至少根据替代级速度计算至少一个成像扫描补偿偏移; 并且根据成像扫描补偿偏移来调整带电粒子束的运动，并以替代阶段速度检查样本，使得带电粒子束紧紧地跟随舞台的运动并且仅图像样本上的采样区域。

5. 发明申请

US20080265251A1 STRUCTURE AND METHOD FOR DETERMINING A DEFECT IN INTEGRATED CIRCUIT MANUFACTURING PROCESS 有权
标题翻译：用于确定集成电路制造过程中的缺陷的结构和方法
公开(公告)号：US20080265251A1
公开(公告)日：2008-10-30
申请号：US12110147
申请日：2008-04-25
申请人： Hong XIAO , Jack Y. JAU , Chang Chun YEH
发明人： Hong XIAO , Jack Y. JAU , Chang Chun YEH
IPC分类号： G01N23/00 , H01L23/58
CPC分类号： H01L22/12 , H01L22/24
摘要： The present invention discloses a structure and method for determining a defect in integrated circuit manufacturing process, wherein the structure comprises a plurality of normal active areas formed in a plurality of first arrays and a plurality of defective active areas formed in a plurality of second arrays. The first arrays and second arrays are interlaced, and the defect is determined by monitoring a voltage contrast from a charged particle microscope image of the active areas.
摘要翻译：本发明公开了一种用于确定集成电路制造过程中的缺陷的结构和方法，其中该结构包括形成在多个第一阵列中的多个正常有源区和形成在多个第二阵列中的多个有缺陷的有源区。第一阵列和第二阵列是交错的，并且通过监视来自有源区域的带电粒子显微镜图像的电压对比来确定缺陷。

6. 发明申请

US20050026310A1 Method for in-line monitoring of via/contact holes etch process based on test structures in semiconductor wafer manufacturing 有权
标题翻译：基于半导体晶片制造中的测试结构的通孔/接触孔蚀刻工艺的在线监测方法
公开(公告)号：US20050026310A1
公开(公告)日：2005-02-03
申请号：US10865230
申请日：2004-06-09
申请人： Yan Zhao , Chang-Chun Yeh , Zhong-Wei Chen , Jack Jau
发明人： Yan Zhao , Chang-Chun Yeh , Zhong-Wei Chen , Jack Jau
IPC分类号： G01L21/30 , H01L21/44 , H01L21/66 , H01L21/768 , H01L23/544
CPC分类号： H01L22/34 , H01L21/76802 , H01L22/24
摘要： A method for in-line monitoring of via/contact etching process based on a test structure is described. The test structure is comprised of via/contact holes of different sizes and densities in a layout such that, for a certain process, the microloading or RIE lag induced non-uniform etch rate produce under-etch in some regions and over-etch in others. A scanning electron microscope is used to distinguish these etching differences in voltage contrast images. Image processing and simple calibration convert these voltage contrast images into a “fingerprint” image characterizing the etching process in terms of thickness over-etched or under-etched. Tolerance of shifting or deformation of this image can be set for validating the process uniformity. This image can also be used as a measure to monitor long-term process parameter shifting, as well as wafer-to-wafer or lot-to-lot variations. Advanced process control (APC) can be performed in-line with the guidance of this image so that potential electrical defects are avoided and process yield ramp accelerated.
摘要翻译：描述了一种基于测试结构进行通孔/接触蚀刻工艺在线监测的方法。测试结构由布局不同尺寸和密度的通孔/接触孔组成，使得对于某些工艺，微加载或RIE滞后引起的不均匀蚀刻速率在一些区域产生蚀刻不良并且在其它区域中过度蚀刻。使用扫描电子显微镜来区分电压对比图像中的这些蚀刻差异。图像处理和简单校准将这些电压对比图像转换成表征蚀刻工艺的“指纹”图像，就厚度过蚀刻或欠蚀刻而言。该图像的偏移或变形的公差可以设置为验证过程的均匀性。该图像也可用作监视长期过程参数移位以及晶圆到晶圆或批次间变化的度量。先进的过程控制（APC）可以与该图像的引导一起进行，以便避免潜在的电气缺陷，加速产出斜率。

7. 发明授权

US07474001B2 Method for in-line monitoring of via/contact holes etch process based on test structures in semiconductor wafer manufacturing 有权
标题翻译：基于半导体晶片制造中的测试结构的通孔/接触孔蚀刻工艺的在线监测方法
公开(公告)号：US07474001B2
公开(公告)日：2009-01-06
申请号：US11452544
申请日：2006-06-13
申请人： Yan Zhao , Chang-Chun Yeh , Zhong-Wei Chen , Jack Jau
发明人： Yan Zhao , Chang-Chun Yeh , Zhong-Wei Chen , Jack Jau
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/76802 , H01L22/26
摘要： A method for in-line monitoring of via/contact etching process based on a test structure is described. The test structure is comprised of via/contact holes of different sizes and densities in a layout such that, for a certain process, the microloading or RIE lag induced non-uniform etch rate produce under-etch in some regions and over-etch in others. A scanning electron microscope is used to distinguish these etching differences in voltage contrast images. Image processing and simple calibration convert these voltage contrast images into a “fingerprint” image characterizing the etching process in terms of thickness over-etched or under-etched. Tolerance of shifting or deformation of this image can be set for validating the process uniformity. This image can also be used as a measure to monitor long-term process parameter shifting, as well as wafer-to-wafer or lot-to-lot variations. Advanced process control (APC) can be performed in-line with the guidance of this image so that potential electrical defects are avoided and process yield ramp accelerated.
摘要翻译：描述了一种基于测试结构进行通孔/接触蚀刻工艺在线监测的方法。测试结构由布局不同尺寸和密度的通孔/接触孔组成，使得对于某些工艺，微加载或RIE滞后引起的不均匀蚀刻速率在一些区域产生蚀刻不良并且在其它区域中过度蚀刻。使用扫描电子显微镜来区分电压对比图像中的这些蚀刻差异。图像处理和简单校准将这些电压对比图像转换成表征蚀刻工艺的“指纹”图像，就厚度过蚀刻或欠蚀刻而言。该图像的偏移或变形的公差可以设置为验证过程的均匀性。该图像也可用作监视长期过程参数移位以及晶圆到晶圆或批次间变化的度量。先进的过程控制（APC）可以与该图像的引导一起进行，以便避免潜在的电气缺陷，加速产出斜率。

8. 发明申请

US20060234496A1 Method for in-line monitoring of via/contact holes etch process based on test structures in semiconductor wafer manufacturing 有权
公开(公告)号：US20060234496A1
公开(公告)日：2006-10-19
申请号：US11452544
申请日：2006-06-13
申请人： Yan Zhao , Chang-Chun Yeh , Zhong-Wei Chen , Jack Jau
发明人： Yan Zhao , Chang-Chun Yeh , Zhong-Wei Chen , Jack Jau
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L22/26
摘要： A method for in-line monitoring of via/contact etching process based on a test structure is described. The test structure is comprised of via/contact holes of different sizes and densities in a layout such that, for a certain process, the microloading or RIE lag induced non-uniform etch rate produce under-etch in some regions and over-etch in others. A scanning electron microscope is used to distinguish these etching differences in voltage contrast images. Image processing and simple calibration convert these voltage contrast images into a “fingerprint” image characterizing the etching process in terms of thickness over-etched or under-etched. Tolerance of shifting or deformation of this image can be set for validating the process uniformity. This image can also be used as a measure to monitor long-term process parameter shifting, as well as wafer-to-wafer or lot-to-lot variations. Advanced process control (APC) can be performed in-line with the guidance of this image so that potential electrical defects are avoided and process yield ramp accelerated.

9. 发明授权

US07105436B2 Method for in-line monitoring of via/contact holes etch process based on test structures in semiconductor wafer manufacturing 有权
公开(公告)号：US07105436B2
公开(公告)日：2006-09-12
申请号：US10865230
申请日：2004-06-09
申请人： Yan Zhao , Chang-Chun Yeh , Zhong-Wei Chen , Jack Jau
发明人： Yan Zhao , Chang-Chun Yeh , Zhong-Wei Chen , Jack Jau
IPC分类号： H01L21/4763
CPC分类号： H01L22/34 , H01L21/76802 , H01L22/24
摘要： A method for in-line monitoring of via/contact etching process based on a test structure is described. The test structure is comprised of via/contact holes of different sizes and densities in a layout such that, for a certain process, the microloading or RIE lag induced non-uniform etch rate produce under-etch in some regions and over-etch in others. A scanning electron microscope is used to distinguish these etching differences in voltage contrast images. Image processing and simple calibration convert these voltage contrast images into a “fingerprint” image characterizing the etching process in terms of thickness over-etched or under-etched. Tolerance of shifting or deformation of this image can be set for validating the process uniformity. This image can also be used as a measure to monitor long-term process parameter shifting, as well as wafer-to-wafer or lot-to-lot variations. Advanced process control (APC) can be performed in-line with the guidance of this image so that potential electrical defects are avoided and process yield ramp accelerated.

10. 发明申请

US20120043462A1 METHOD AND APPARATUS FOR CHARGED PARTICLE BEAM INSPECTION 有权
标题翻译：充电粒子束检测方法和装置
公开(公告)号：US20120043462A1
公开(公告)日：2012-02-23
申请号：US13288563
申请日：2011-11-03
申请人： Chang Chun YEH , Shih-Tsuan CHANG
发明人： Chang Chun YEH , Shih-Tsuan CHANG
IPC分类号： G01N23/00
CPC分类号： H01J37/28 , H01J37/20 , H01J37/265 , H01J2237/20228 , H01J2237/2817
摘要： A method, apparatus and computer readable medium for charged particle beam inspection of a sample comprising at least one sampling region and at least one skip region is disclosed. The method, apparatus and computer readable medium comprise receiving an imaging recipe which at least comprises information of the area of the sampling and skip regions; calculating a default stage speed according to the imaging recipe; calculating an alternative stage speed at least according to the default stage speed, the sampling region area information, and the skip region area information; calculating at least one imaging scan compensation offset at least according to the alternative stage speed; and inspecting the sample at the alternative stage speed while adjusting the motion of the charged particle beam according to the imaging scan compensation offsets, such that the charged particle beam tightly follows the motion of the stage and images only the sampling regions on the sample.
摘要翻译：公开了一种用于对包含至少一个采样区域和至少一个跳过区域的样本进行带电粒子束检查的方法，装置和计算机可读介质。该方法，装置和计算机可读介质包括接收至少包括采样和跳过区域的区域的信息的成像配方; 根据成像配方计算默认舞台速度; 至少根据默认级速度，采样区域信息和跳过区域区域信息计算替代级速度; 至少根据替代级速度计算至少一个成像扫描补偿偏移; 并且根据成像扫描补偿偏移来调整带电粒子束的运动，并以替代级速度检查样品，使得带电粒子束紧紧地跟随载物台的运动并且仅图像样品上的取样区域。

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