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1. 发明申请

US20080170450A1 METHOD FOR TESTING INTERNAL HIGH VOLTAGE IN NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND RELATED VOLTAGE OUTPUT CIRCUIT 失效
标题翻译：在非易失性半导体存储器件和相关电压输出电路中测试内部高电压的方法
公开(公告)号：US20080170450A1
公开(公告)日：2008-07-17
申请号：US11957808
申请日：2007-12-17
申请人： Chae-Hoon KIM , Dae-Han KIM
发明人： Chae-Hoon KIM , Dae-Han KIM
IPC分类号： G11C29/50 , G11C16/06
CPC分类号： G11C16/30 , G11C5/145 , G11C16/04 , G11C27/024 , G11C29/02 , G11C29/021
摘要： In a voltage output circuit of a nonvolatile semiconductor memory device, a high voltage generator generates an internal high voltage, a sampling signal generator generates a sampling signal, and a sample and old circuit samples and holds the internal high voltage in accordance with the sampling signal.
摘要翻译：在非易失性半导体存储器件的电压输出电路中，高电压发生器产生内部高电压，采样信号发生器产生采样信号，采样和旧电路采样并根据采样信号保持内部高电压。

2. 发明授权

US08347183B2 Flash memory device using ECC algorithm and method of operating the same 有权
标题翻译：闪存设备使用ECC算法和操作方法相同
公开(公告)号：US08347183B2
公开(公告)日：2013-01-01
申请号：US12486875
申请日：2009-06-18
申请人： Chi-weon Yoon , Chae-hoon Kim
发明人： Chi-weon Yoon , Chae-hoon Kim
IPC分类号： H03M13/00
CPC分类号： G06F11/1068 , G11C16/16 , G11C16/3454
摘要： A flash memory device using an error correction code (ECC) algorithm and a method of operating the same. The device includes a memory cell array including a error correction code (ECC) block including data memory cells configured to store data and a parity cell configured to store a first parity code, a parity controller configured to generate a second parity code based on a the current operating mode of the flash memory device, and an error correction unit configured to receive one of the first and second parity codes and to perform an ECC algorithm on the data stored in the data memory cells using the received parity code. A control logic restarts an erase operation on an erroneously unerased data memory cell or prevents the erase operation from being restarted based on the number of erroneous bits per ECC block.
摘要翻译：一种使用纠错码（ECC）算法的闪存器件及其操作方法。该设备包括存储单元阵列，其包括纠错码（ECC）块，该纠错码（ECC）块包括被配置为存储数据的数据存储器单元和被配置为存储第一奇偶校验码的奇偶校验单元，奇偶校验控制器被配置为基于闪存器件的当前操作模式，以及错误校正单元，被配置为接收第一和第二奇偶校验码之一，并且使用所接收的奇偶校验码对存储在数据存储单元中的数据执行ECC算法。一个控制逻辑重新启动一个错误的未故障的数据存储单元上的擦除操作，或者基于每个ECC块的错误位数来防止重新启动擦除操作。

3. 发明授权

US07729173B2 Method for testing internal high voltage in nonvolatile semiconductor memory device and related voltage output circuit 失效
标题翻译：用于在非易失性半导体存储器件和相关电压输出电路中测试内部高电压的方法
公开(公告)号：US07729173B2
公开(公告)日：2010-06-01
申请号：US11957808
申请日：2007-12-17
申请人： Chae-Hoon Kim , Dae-Han Kim
发明人： Chae-Hoon Kim , Dae-Han Kim
IPC分类号： G11C11/34 , G11C5/14 , G11C8/00
CPC分类号： G11C16/30 , G11C5/145 , G11C16/04 , G11C27/024 , G11C29/02 , G11C29/021
摘要： In a voltage output circuit of a nonvolatile semiconductor memory device, a high voltage generator generates an internal high voltage, a sampling signal generator generates a sampling signal, and a sample and old circuit samples and holds the internal high voltage in accordance with the sampling signal.
摘要翻译：在非易失性半导体存储器件的电压输出电路中，高电压发生器产生内部高电压，采样信号发生器产生采样信号，采样和旧电路采样并根据采样信号保持内部高电压。

4. 发明授权

US07697340B2 Methods and apparatuses for trimming reference cells in semiconductor memory devices 失效
标题翻译：用于修整半导体存储器件中的参考单元的方法和装置
公开(公告)号：US07697340B2
公开(公告)日：2010-04-13
申请号：US11806587
申请日：2007-06-01
申请人： Chae-Hoon Kim , Dae-Han Kim
发明人： Chae-Hoon Kim , Dae-Han Kim
IPC分类号： G11C11/34
CPC分类号： G11C5/143 , G11C16/20 , G11C29/02 , G11C29/026 , G11C29/028 , G11C29/24 , G11C29/50 , G11C2029/5006
摘要： A method and apparatus for trimming a reference cell in a semiconductor memory device are provided. The method includes generating an internal bias current capable of being trimmed, and trimming the reference cell based on the internal bias current. The semiconductor memory device includes a reference cell in which a reference cell current flows between a drain and a source based on a bias voltage, an internal bias current generator configured to generate an internal bias current capable of being trimmed, and a trimming circuit configured to trim the reference cell based on the internal bias current.
摘要翻译：提供了一种用于修整半导体存储器件中的参考单元的方法和装置。该方法包括产生能够被修整的内部偏置电流，以及基于内部偏置电流来修整参考单元。半导体存储器件包括参考单元，其中参考单元电流基于偏置电压在漏极和源极之间流动;内部偏置电流发生器，被配置为产生能够被修整的内部偏置电流;以及微调电路，其被配置为基于内部偏置电流修整参考单元。

5. 发明申请

US20090327839A1 FLASH MEMORY DEVICE USING ECC ALGORITHM AND METHOD OF OPERATING THE SAME 有权
标题翻译：使用ECC算法的闪存存储器件及其操作方法
公开(公告)号：US20090327839A1
公开(公告)日：2009-12-31
申请号：US12486875
申请日：2009-06-18
申请人： Chi-weon Yoon , Chae-hoon Kim
发明人： Chi-weon Yoon , Chae-hoon Kim
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1068 , G11C16/16 , G11C16/3454
摘要： A flash memory device using an error correction code (ECC) algorithm and a method of operating the same. The device includes a memory cell array including a error correction code (ECC) block including data memory cells configured to store data and a parity cell configured to store a first parity code, a parity controller configured to generate a second parity code based on a the current operating mode of the flash memory device, and an error correction unit configured to receive one of the first and second parity codes and to perform an ECC algorithm on the data stored in the data memory cells using the received parity code. A control logic restarts an erase operation on an erroneously unerased data memory cell or prevents the erase operation from being restarted based on the number of erroneous bits per ECC block.
摘要翻译：一种使用纠错码（ECC）算法的闪存器件及其操作方法。该设备包括存储单元阵列，其包括纠错码（ECC）块，该纠错码（ECC）块包括被配置为存储数据的数据存储器单元和被配置为存储第一奇偶校验码的奇偶校验单元，奇偶校验控制器被配置为基于闪存器件的当前操作模式，以及错误校正单元，被配置为接收第一和第二奇偶校验码之一，并且使用所接收的奇偶校验码对存储在数据存储单元中的数据执行ECC算法。一个控制逻辑重新启动一个错误的未故障的数据存储单元上的擦除操作，或者基于每个ECC块的错误位数来防止重新启动擦除操作。

6. 发明申请

US20080137433A1 Methods and apparatuses for trimming reference cells in semiconductor memory devices 失效
标题翻译：用于修整半导体存储器件中的参考单元的方法和装置
公开(公告)号：US20080137433A1
公开(公告)日：2008-06-12
申请号：US11806587
申请日：2007-06-01
申请人： Chae-Hoon Kim , Dae-Han Kim
发明人： Chae-Hoon Kim , Dae-Han Kim
IPC分类号： G11C11/34
CPC分类号： G11C5/143 , G11C16/20 , G11C29/02 , G11C29/026 , G11C29/028 , G11C29/24 , G11C29/50 , G11C2029/5006
摘要： A method and apparatus for trimming a reference cell in a semiconductor memory device are provided. The method includes generating an internal bias current capable of being trimmed, and trimming the reference cell based on the internal bias current. The semiconductor memory device includes a reference cell in which a reference cell current flows between a drain and a source based on a bias voltage, an internal bias current generator configured to generate an internal bias current capable of being trimmed, and a trimming circuit configured to trim the reference cell based on the internal bias current.
摘要翻译：提供了一种用于修整半导体存储器件中的参考单元的方法和装置。该方法包括产生能够被修整的内部偏置电流，以及基于内部偏置电流来修整参考单元。半导体存储器件包括参考单元，其中参考单元电流基于偏置电压在漏极和源极之间流动;内部偏置电流发生器，被配置为产生能够被修整的内部偏置电流;以及微调电路，其被配置为基于内部偏置电流修整参考单元。

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