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1. 发明申请

WO2014084905A1 SYSTEM, METHOD, AND APPARATUS FOR IMPROVING THROUGHPUT OF CONSECUTIVE TRANSACTIONAL MEMORY REGIONS 审中-公开
标题翻译：系统，方法和装置，用于改善交互式存储器区域的通过
公开(公告)号：WO2014084905A1
公开(公告)日：2014-06-05
申请号：PCT/US2013/045982
申请日：2013-06-14
申请人： INTEL CORPORATION , SHAIKH, Omar M. , RAJWAR, Ravi , CAPRIOLI, Paul , AL-OTOOM, Muawya M.
发明人： SHAIKH, Omar M. , RAJWAR, Ravi , CAPRIOLI, Paul , AL-OTOOM, Muawya M.
IPC分类号： G06F12/02
CPC分类号： G06F9/3855 , G06F9/3004 , G06F9/30043 , G06F9/3016 , G06F9/3802 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3863 , G06F9/467 , G06F11/1448 , G06F11/1469 , G06F12/0828 , G06F12/084 , G06F12/0842 , G06F12/0875 , G06F2201/84 , G06F2212/1016 , G06F2212/452 , G06F2212/507 , G06F2212/6042 , G06F2212/62 , G06F2212/621 , G06F2213/0026
摘要： Systems, apparatuses, and methods for improving TM throughput using a TM region indicator (or color) are described. Through the use of TM region indicators younger TM regions can have their instructions retired while waiting for older TM regions to commit.
摘要翻译：描述了使用TM区域指示符（或颜色）来提高TM吞吐量的系统，装置和方法。通过使用TM区域指标，年龄较小的TM区域可以在等待旧TM区域提交时，退出指令。

2. 发明申请

WO2013085518A1 A METHOD, APPARATUS, AND SYSTEM FOR EFFICIENTLY HANDLING MULTIPLE VIRTUAL ADDRESS MAPPINGS DURING TRANSACTIONAL EXECUTION 审中-公开
标题翻译：在交易执行期间有效处理多个虚拟地址映射的方法，装置和系统
公开(公告)号：WO2013085518A1
公开(公告)日：2013-06-13
申请号：PCT/US2011/063888
申请日：2011-12-08
申请人： INTEL CORPORATION , CAPRIOLI, Paul , KANHERE, Abhay S.
发明人： CAPRIOLI, Paul , KANHERE, Abhay S.
IPC分类号： G06F12/10 , G06F9/06
CPC分类号： G06F12/10 , G06F9/528 , G06F12/1027
摘要： An apparatus and method is described herein for providing structures to support software memory re-ordering within atomic sections of code. Upon a start or end of a critical section, speculative bits of a translation buffer are reset. When a speculative memory access causes an address translation of a virtual address to a physical address, the translation buffer is searched to determine if another entry (a different virtual address) includes the same physical address. And if another entry does include the same physical address, the speculative execution is failed to provide protection from invalid execution resulting from the memory re-ordering.
摘要翻译：本文描述了一种装置和方法，用于提供结构以支持代码的原子部分内的软件存储器重新排序。在关键部分的开始或结束时，翻译缓冲器的推测位被重置。当推测存储器访问导致虚拟地址到物理地址的地址转换时，搜索翻译缓冲器以确定另一个条目（不同的虚拟地址）是否包括相同的物理地址。而如果另一个条目包含相同的物理地址，那么推测性执行就无法提供保护，避免因内存重新排序导致的无效执行。

3. 发明申请

WO2013048460A1 INSTRUCTION AND LOGIC TO CONTROL TRANSFER IN A PARTIAL BINARY TRANSLATION SYSTEM 审中-公开
标题翻译：指导和逻辑控制部分二进制翻译系统的转移
公开(公告)号：WO2013048460A1
公开(公告)日：2013-04-04
申请号：PCT/US2011/054355
申请日：2011-09-30
申请人： INTEL CORPORATION , CAPRIOLI, Paul , DIXON, Martin, G. , TOLL, Brett, L. , AL-OTOOM, Muawya, M. , SHAIKH, Omar
发明人： CAPRIOLI, Paul , DIXON, Martin, G. , TOLL, Brett, L. , AL-OTOOM, Muawya, M. , SHAIKH, Omar
IPC分类号： G06F9/45
CPC分类号： G06F9/30043 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/3808 , G06F9/3877 , G06F9/3887
摘要： A dynamic optimization of code for a processor-specific dynamic binary translation of hot code pages (e.g., frequently executed code pages) may be provided by a run-time translation layer. A method may be provided to use an instruction look aside buffer (iTLB) to map original code pages and translated code pages. The method may comprise fetching an instruction from an original code page, determining whether the fetched instruction is a first instruction of a new code page and whether the original code page is deprecated. If both determinations return yes, the method may further comprise fetching a next instruction from a translated code page. If either determinations returns no, the method may further comprise decoding the instruction and fetching the next instruction from the original code page.
摘要翻译：可以由运行时转换层提供用于热代码页（例如，经常执行的代码页）的处理器特定的动态二进制转换的代码的动态优化。可以提供一种方法来使用缓冲器（iTLB）的指令来映射原始代码页和转换的代码页。该方法可以包括从原始代码页获取指令，确定所提取的指令是否是新代码页的第一指令以及原始代码页是否已被弃用。如果两个确定返回是，该方法还可以包括从转换的代码页获取下一个指令。如果任一确定返回否，则该方法还可以包括解码指令并从原始代码页获取下一条指令。

4. 发明申请

WO2007092281A3 METHOD AND APPARATUS FOR SIMULTANEOUS SPECULATIVE THREADING 审中-公开
标题翻译：同时测量螺旋线的方法和装置
公开(公告)号：WO2007092281A3
公开(公告)日：2007-09-27
申请号：PCT/US2007002830
申请日：2007-02-02
申请人： SUN MICROSYSTEMS INC , CHAUDHRY SHAILENDER , TREMBLAY MARC , CAPRIOLI PAUL
发明人： CHAUDHRY SHAILENDER , TREMBLAY MARC , CAPRIOLI PAUL
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/383 , G06F9/3842 , G06F9/3863
摘要： One embodiment of the present invention provides a system which performs simultaneous speculative threading. The system starts by executing instructions in normal execution mode using a first thread. Upon encountering a data-dependent stall condition, the first thread generates an architectural checkpoint and commences execution of instructions in execute-ahead mode. During execute-ahead mode, the first thread executes instructions that can be executed and defers instructions that cannot be executed into a deferred queue. When the data dependent stall condition has been resolved, the first thread generates a speculative checkpoint and continues execution in execute-ahead mode. At the same time, the second thread commences execution in a deferred mode, wherein the second thread executes instructions deferred by the first thread.
摘要翻译：本发明的一个实施例提供一种执行同时投机线程的系统。系统通过使用第一个线程在正常执行模式下执行指令来启动。在遇到数据相关的停顿条件时，第一个线程生成架构检查点，并以执行提前模式开始执行指令。在执行提前模式期间，第一个线程执行可执行的指令，并将不能执行的指令拖到延迟队列中。当数据相关的停顿条件已经解决时，第一个线程生成一个推测性检查点，并以执行提前模式继续执行。同时，第二线程以延迟模式开始执行，其中第二线程执行由第一线程延迟的指令。

5. 发明申请

WO2006016927A3 SELECTIVE EXECUTION OF DEFERRED INSTRUCTIONS 审中-公开
标题翻译：删减指示的选择性执行
公开(公告)号：WO2006016927A3
公开(公告)日：2006-12-07
申请号：PCT/US2005016433
申请日：2005-05-11
申请人： SUN MICROSYSTEMS INC , CHAUDHRY SHAILENDER , CAPRIOLI PAUL , TREMBLAY MARC
发明人： CHAUDHRY SHAILENDER , CAPRIOLI PAUL , TREMBLAY MARC
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/30181 , G06F9/30189 , G06F9/3838 , G06F9/3842 , G06F9/3857
摘要： A system which selectively executes deferred instructions following a return of a long-latency operation in a processor that supports speculative-execution. When the processor encounters a long-latency operation, the processor records the long-latency operation in a long-latency scoreboard, wherein each entry in the long-latency scoreboard includes a deferred buffer start index. Upon encountering an unresolved data dependency, the processor performs a checkpointing operation and executes subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of the unresolved data dependency are deferred into a deferred buffer, and wherein other non-deferred instructions are executed in program order. Upon encountering a deferred instruction that depends on a long-latency operation within the long-latency scoreboard, the processor updates a deferred buffer start index associated with the long-latency operation to point to position in the deferred buffer occupied by the deferred instruction. When a long-latency operation returns, the processor executes instructions in the deferred buffer starting at the deferred buffer start index for the returning long-latency operation.
摘要翻译：在支持推测执行的处理器中的长延迟操作返回之后有选择地执行延迟指令的系统。当处理器遇到长时间延迟操作时，处理器将长延迟操作记录在长时间延迟记分板中，其中长延迟记分板中的每个条目包括延迟缓冲区起始索引。在遇到未解决的数据依赖性时，处理器执行检查点操作并以执行模式执行后续指令，其中由于未解决的数据相关性而不能执行的指令被推迟到延迟缓冲器中，并且其中其他非延迟指令以程序顺序执行。在遇到取决于长延迟记分板中的长时间延迟操作的延迟指令时，处理器更新与长延迟操作相关联的延迟缓冲器开始索引以指向由延迟指令占用的延迟缓冲器中的位置。当长延迟操作返回时，处理器执行延迟缓冲区中的指令，从延迟缓冲区起始索引开始，用于返回长延迟操作。

6. 发明申请

WO2006001946A3 METHOD FOR IMPROVED REISSUE OF DEFERRED INSTRUCTIONS 审中-公开
标题翻译：改进指示的方法
公开(公告)号：WO2006001946A3
公开(公告)日：2006-11-02
申请号：PCT/US2005017454
申请日：2005-05-18
申请人： SUN MICROSYSTEMS INC , CHAUDRY SHAILENDER , CAPRIOLI PAUL , TREMBLAY MARC
发明人： CHAUDRY SHAILENDER , CAPRIOLI PAUL , TREMBLAY MARC
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3842 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F9/3863
摘要： One embodiment of the present invention provides a system which facilitates eliminating a restart penalty when reissuing deferred instructions in a processor that supports speculative-execution. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the processor performs a checkpointing operation and executes subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of the unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order. When an unresolved data dependency is resolved during execute-ahead mode, the processor begins to execute the deferred instructions in a deferred mode. In doing so, the processor initially issues deferred instructions, which have already been decoded, from a deferred queue. Simultaneously, the processor feeds instructions from a deferred SRAM into the decode unit, and these instructions eventually pass into the deferred queue.
摘要翻译：本发明的一个实施例提供了一种在支持推测执行的处理器中重新发布延迟指令时有助于消除重新开始惩罚的系统。在正常执行模式下，系统以程序顺序发出执行指令。在执行指令期间遇到未解决的数据依赖性时，处理器执行检查点操作并以执行模式执行后续指令，其中由于未解决的数据依赖性而不能执行的指令被推迟，并且其中其他非延迟指令以程序顺序执行。当在执行提前模式期间解决未解决的数据依赖关系时，处理器以延迟模式开始执行延迟指令。在这样做时，处理器最初从延迟队列中发出已被解码的延迟指令。同时，处理器将来自延迟SRAM的指令送入解码单元，并且这些指令最终进入延迟队列。

7. 发明申请

WO2006081049A3 IMPROVING BRANCH PREDICTION ACCURACY IN A PROCESSOR THAT SUPPORTS SPECULATIVE EXECUTION 审中-公开
公开(公告)号：WO2006081049A3
公开(公告)日：2006-08-03
申请号：PCT/US2006/000354
申请日：2006-01-05
申请人： SUN MICROSYSTEMS, INC. , CAPRIOLI, Paul , YIP, Sherman, H. , CHAUDHRY, Shailender
发明人： CAPRIOLI, Paul , YIP, Sherman, H. , CHAUDHRY, Shailender
IPC分类号： G06F9/38
摘要： One embodiment of the present invention provides a system which improves branch prediction accuracy in a processor that supports speculative-execution. During normal-execution mode, the system issues instructions in program order. Upon encountering a launch condition which causes a processor to enter a speculative-execution mode, the system performs a checkpoint and begins executing instructions in a speculative-execution mode. Upon encountering a branch instruction during speculative-execution mode, the system selects the subsequent instruction to be executed based on a current state of a branch predictor and does not update the current state of the branch predictor, thereby preventing the branch predictor from being incorrectly updated twice when re-executing the branch instruction after returning to normal-execution mode.

8. 发明申请

WO2006004575A2 METHOD AND APPARATUS FOR AVOIDING RAW HAZARDS IN AN EXECUTE-AHEAD PROCESSOR 审中-公开
标题翻译：用于避免执行前处理器中的原始危险的方法和设备
公开(公告)号：WO2006004575A2
公开(公告)日：2006-01-12
申请号：PCT/US2005/005699
申请日：2005-02-23
申请人： SUN MICROSYSTEMS, INC. , CHAUDHRY, Shaildender , CAPRIOLI, Paul , TREMBLAY, Marc
发明人： CHAUDHRY, Shaildender , CAPRIOLI, Paul , TREMBLAY, Marc
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/30189 , G06F9/383 , G06F9/3838 , G06F9/3863
摘要： One embodiment of the present invention provides a system that avoids read-after-write (RAW) hazards while speculatively executing instructions on a processor. The system starts in a normal execution mode, wherein the system issues instructions for the execution in program order. Upon encountering a stall condition during execution of an instruction, the system generates a checkpoint, and executes the instruction and subsequent instruction in a speculative-execution mode. The system also maintains dependency information for each register indication whether or not a value in the register depends on an unresolved data-dependency. The system uses this dependency information to avoid RAW hazards during the speculative-execution mode.
摘要翻译：本发明的一个实施例提供了一种系统，该系统在推测性地执行处理器上的指令的同时避免了写后读（RAW）危害。系统以正常执行模式启动，其中系统按程序顺序发出执行指令。在执行指令期间遇到停顿条件时，系统产生检查点，并在推测执行模式下执行该指令和随后的指令。系统还维护每个寄存器指示的依赖性信息，无论寄存器中的值是否取决于未解决的数据相关性。系统在推测执行模式下使用此依赖性信息来避免RAW危害。

9. 发明申请

WO2005093563A2 METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING THE AGGRESSIVENESS OF AN EXECUTE-AHEAD PROCESSOR 审中-公开
标题翻译：用于动态调整执行前处理器的方法和装置的方法和装置
公开(公告)号：WO2005093563A2
公开(公告)日：2005-10-06
申请号：PCT/US2005/009156
申请日：2005-03-18
申请人： SUN MICROSYSTEMS, INC. , CAPRIOLI, Paul , YIP, Sherman
发明人： CAPRIOLI, Paul , YIP, Sherman
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/30181 , G06F9/30189 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： One embodiment of the present invention provides a system that dynamically adjusts the aggressiveness of an execute-ahead processor. If a data-dependent stall condition is encountered during program execution, the system enters an execute-ahead mode, wherein instructions that cannot be executed because of the unresolved data dependency are deferred, and other non-deferred instructions are executed in program order. If a non-data-dependent stall condition is encountered during execute-ahead mode, the system enters a scout mode, wherein instructions are speculatively executed to prefetch future loads, but results are not committed to the architectural state of the execute-ahead processor. On the other had, if an unresolved data dependency is resolved during the execute-ahead mode, enters a deferred mode and executes deferred instructions. During this deferred mode, if some instructions are deferred again, the system determines whether to resume execution in the execute-ahead mode. If it determines to do so, the system resumes execution in the execute-ahead mode, and otherwise resumes execution in a non-aggressive mode.
摘要翻译：本发明的一个实施例提供了一种动态地调整执行前处理器的侵略性的系统。如果在程序执行期间遇到与数据有关的失速条件，则系统进入执行模式，其中由于未解决的数据相关性而无法执行的指令被延迟，并且其他非延迟指令以程序顺序执行。如果在执行提前模式期间遇到非数据相关的失速条件，则系统进入侦察模式，其中，推测性地执行指令以预取未来的负载，但是结果并未提交到执行前处理器的架构状态。另一方面，如果在执行提前模式下解决了未解决的数据依赖关系，则进入延迟模式并执行延迟指令。在该延迟模式期间，如果再次延迟某些指令，则系统确定是否在执行模式下继续执行。如果它确定这样做，系统将以执行方式恢复执行，否则以非侵略模式恢复执行。

10. 发明申请

WO2005093563A3 METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING THE MODE OF AN EXECUTE-AHEAD PROCESSOR 审中-公开
标题翻译：用于动态调整执行前处理器模式的方法和装置
公开(公告)号：WO2005093563A3
公开(公告)日：2006-06-01
申请号：PCT/US2005009156
申请日：2005-03-18
申请人： SUN MICROSYSTEMS INC , CAPRIOLI PAUL , YIP SHERMAN
发明人： CAPRIOLI PAUL , YIP SHERMAN
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3842 , G06F9/30181 , G06F9/30189 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： One embodiment of the present invention provides a system that dynamically adjusts the aggressiveness of an execute-ahead processor. If a data-dependent stall condition is encountered during program execution, the system enters an execute-ahead mode, wherein instructions that cannot be executed because of the unresolved data dependency are deferred, and other non-deferred instructions are executed in program order. If a non-data-dependent stall condition is encountered during execute-ahead mode, the system enters a scout mode, wherein instructions are speculatively executed to prefetch future loads, but results are not committed to the architectural state of the execute-ahead processor. On the other had, if an unresolved data dependency is resolved during the execute-ahead mode, enters a deferred mode and executes deferred instructions. During this deferred mode, if some instructions are deferred again, the system determines whether to resume execution in the execute-ahead mode. If it determines to do so, the system resumes execution in the execute-ahead mode, and otherwise resumes execution in a non-aggressive mode.
摘要翻译：本发明的一个实施例提供了一种动态地调整执行前处理器的侵略性的系统。如果在程序执行期间遇到与数据有关的失速条件，则系统进入执行模式，其中由于未解决的数据相关性而无法执行的指令被延迟，并且其他非延迟指令以程序顺序执行。如果在执行提前模式期间遇到非数据相关的失速条件，则系统进入侦察模式，其中，推测性地执行指令以预取未来的负载，但是结果并未提交到执行前处理器的架构状态。另一方面，如果在执行提前模式下解决了未解决的数据依赖关系，则进入延迟模式并执行延迟指令。在该延迟模式期间，如果再次延迟某些指令，则系统确定是否在执行模式下继续执行。如果它确定这样做，系统将以执行方式恢复执行，否则以非侵略模式恢复执行。

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