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1. 发明授权

US08329523B2 Array substrate for dislay device and method of fabricating the same 有权
标题翻译：阵列衬底及其制造方法
公开(公告)号：US08329523B2
公开(公告)日：2012-12-11
申请号：US12654584
申请日：2009-12-23
申请人： Hee-Dong Choi , Ki-Sul Cho , Hye-Young Choi , Doo-Seok Yang , Byeong-Gyu Roh
发明人： Hee-Dong Choi , Ki-Sul Cho , Hye-Young Choi , Doo-Seok Yang , Byeong-Gyu Roh
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L27/1288 , G02F2001/136236 , H01L21/02532 , H01L21/02667 , H01L27/1214 , H01L27/1218 , H01L27/124 , H01L27/3244 , H01L29/42384 , H01L29/458 , H01L29/66765 , H01L2227/323
摘要： A method of fabricating an array substrate for a display device includes: forming a buffer layer on a substrate having a pixel region; sequentially forming a gate electrode of impurity-doped polycrystalline silicon, a gate insulating layer and an active layer of intrinsic polycrystalline silicon on the buffer layer in the pixel region; forming an interlayer insulating layer of an inorganic insulating material on the active layer; sequentially forming a source barrier pattern, a source ohmic contact layer and a source electrode on the interlayer insulating layer, sequentially forming a drain barrier pattern, a drain ohmic contact layer and a drain electrode on the interlayer insulating layer, and sequentially forming a first dummy pattern, a second dummy pattern and a data line on the interlayer insulating layer; forming a first passivation layer on a surface of the interlayer insulating layer including the source electrode, the drain electrode and the data line formed thereon; forming a gate line on the first passivation layer; forming a second passivation layer on a surface of the first passivation layer including the gate line formed thereon; and forming a pixel electrode on the second passivation layer.
摘要翻译：一种制造用于显示装置的阵列基板的方法包括：在具有像素区域的基板上形成缓冲层; 在像素区域的缓冲层上依次形成杂质掺杂多晶硅的栅电极，栅极绝缘层和本征多晶硅的有源层; 在有源层上形成无机绝缘材料的层间绝缘层; 在层间绝缘层上顺序地形成源极阻挡图案，源极欧姆接触层和源电极，在层间绝缘层上依次形成漏极阻挡图案，漏极欧姆接触层和漏极，并依次形成第一虚拟图案，第二虚设图案和数据线; 在包括形成在其上的源电极，漏电极和数据线的层间绝缘层的表面上形成第一钝化层; 在所述第一钝化层上形成栅极线; 在包括形成在其上的栅极线的第一钝化层的表面上形成第二钝化层; 以及在所述第二钝化层上形成像素电极。

2. 发明申请

US20100289023A1 Array substrate for dislay device and method of fabricating the same 有权
标题翻译：阵列衬底及其制造方法
公开(公告)号：US20100289023A1
公开(公告)日：2010-11-18
申请号：US12654584
申请日：2009-12-23
申请人： Hee-Dong Choi , Ki-Sul Cho , Hye-Young Choi , Doo-Seok Yang , Byeong-Gyu Roh
发明人： Hee-Dong Choi , Ki-Sul Cho , Hye-Young Choi , Doo-Seok Yang , Byeong-Gyu Roh
IPC分类号： H01L33/00 , H01L21/336
CPC分类号： H01L27/1288 , G02F2001/136236 , H01L21/02532 , H01L21/02667 , H01L27/1214 , H01L27/1218 , H01L27/124 , H01L27/3244 , H01L29/42384 , H01L29/458 , H01L29/66765 , H01L2227/323
摘要： A method of fabricating an array substrate for a display device includes: forming a buffer layer on a substrate having a pixel region; sequentially forming a gate electrode of impurity-doped polycrystalline silicon, a gate insulating layer and an active layer of intrinsic polycrystalline silicon on the buffer layer in the pixel region; forming an interlayer insulating layer of an inorganic insulating material on the active layer; sequentially forming a source barrier pattern, a source ohmic contact layer and a source electrode on the interlayer insulating layer, sequentially forming a drain barrier pattern, a drain ohmic contact layer and a drain electrode on the interlayer insulating layer, and sequentially forming a first dummy pattern, a second dummy pattern and a data line on the interlayer insulating layer; forming a first passivation layer on a surface of the interlayer insulating layer including the source electrode, the drain electrode and the data line formed thereon; forming a gate line on the first passivation layer; forming a second passivation layer on a surface of the first passivation layer including the gate line formed thereon; and forming a pixel electrode on the second passivation layer.
摘要翻译：一种制造用于显示装置的阵列基板的方法包括：在具有像素区域的基板上形成缓冲层; 在像素区域的缓冲层上依次形成杂质掺杂多晶硅的栅电极，栅极绝缘层和本征多晶硅的有源层; 在有源层上形成无机绝缘材料的层间绝缘层; 在层间绝缘层上顺序地形成源极阻挡图案，源极欧姆接触层和源电极，在层间绝缘层上依次形成漏极阻挡图案，漏极欧姆接触层和漏极，并依次形成第一虚拟图案，第二虚设图案和数据线; 在包括形成在其上的源极电极，漏极电极和数据线的层间绝缘层的表面上形成第一钝化层; 在所述第一钝化层上形成栅极线; 在包括形成在其上的栅极线的第一钝化层的表面上形成第二钝化层; 以及在所述第二钝化层上形成像素电极。

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