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1. 发明授权

US5835946A High performance implementation of the load reserve instruction in a superscalar microprocessor that supports multi-level cache organizations 失效
标题翻译：在支持多级缓存组织的超标量微处理器中高性能地执行负载预留指令
公开(公告)号：US5835946A
公开(公告)日：1998-11-10
申请号：US634907
申请日：1996-04-18
申请人： Michael S. Allen , Brad B. Beavers , Robert Alan Cargnoni , Jose Melanio Nunez , David W. Todd , Jen-Tian Yen
发明人： Michael S. Allen , Brad B. Beavers , Robert Alan Cargnoni , Jose Melanio Nunez , David W. Todd , Jen-Tian Yen
IPC分类号： G06F9/312 , G06F12/08 , G06F12/00 , G06F13/00
CPC分类号： G06F9/3004 , G06F12/0875 , G06F9/30087 , G06F12/0897
摘要： The present invention provides a system and method for efficient execution of load reserve (LARX) and store conditional (STCX) instructions in a superscalar processor. A system for efficiently providing a LARX instruction in a superscalar processor is disclosed. The system comprises a data cache (Dcache) for receiving the LARX instruction. The data cache further includes a decoder means for setting and resetting of a validation of the load reserve instruction, an internal cache for receiving address information and for providing data. The system also includes a register means for receiving the LARX instruction and a controller means for providing a physical address based upon the address information. The system provides for the validation being accomplished in one cycle for the LARX instruction when there is a hit on the internal data cache.
摘要翻译：本发明提供了一种用于在超标量处理器中有效执行负载储备（LARX）和存储条件（STCX）指令的系统和方法。公开了一种用于在超标量处理器中有效提供LARX指令的系统。该系统包括用于接收LARX指令的数据高速缓存（Dcache）。数据高速缓存还包括用于设置和重置负载保留指令的验证的解码器装置，用于接收地址信息并用于提供数据的内部高速缓存。该系统还包括用于接收LARX指令的寄存器装置和用于基于地址信息提供物理地址的控制器装置。当在内部数据高速缓存上存在命中时，系统提供在LARX指令的一个周期内完成的验证。

2. 发明授权

US5682495A Fully associative address translation buffer having separate segment and page invalidation 失效
标题翻译：完全关联地址转换缓冲区具有单独的段和页面无效
公开(公告)号：US5682495A
公开(公告)日：1997-10-28
申请号：US353007
申请日：1994-12-09
申请人： Brad B. Beavers , Lew Chua-Eoan , Pei-Chun Peter Liu , Chih-Jui Peng
发明人： Brad B. Beavers , Lew Chua-Eoan , Pei-Chun Peter Liu , Chih-Jui Peng
IPC分类号： G06F12/10
CPC分类号： G06F12/1036
摘要： A fully associative address translator which includes a number of entries, each of said number of entries translating a received effective address into a real address, each received effective address including a segment identifier and a page identifier. Each of the entries within the fully associative address translator includes a first translation from an effective address segment identifier into a virtual address segment identifier and a second translation from a virtual address page identifier to a real address page identifier. A first valid bit cell is provided for storing a validity bit which indicates the validity of the first translation from the effective address segment identifier to the virtual address segment identifier and a second valid bit cell is also provided for storing a validity bit indicating the validity of the second translation from the virtual address page identifier to the real address page identifier wherein a process context switch will invalidate only a portion of each of the entries, thereby reducing the miss penalty associated with a context switch.
摘要翻译：一种完全关联地址转换器，其包括多个条目，所述数量的条目中的每一个将接收的有效地址转换为实际地址，每个接收到的有效地址包括段标识符和页面标识符。完全关联地址转译器中的每个条目包括从有效地址段标识符到虚拟地址段标识符的第一转换和从虚拟地址页标识符到真实地址页标识符的第二转换。提供第一有效比特单元，用于存储指示从有效地址段标识符到虚拟地址段标识符的第一翻译的有效性的有效位，并且还提供第二有效位单元，用于存储指示有效位的有效位从虚拟地址页标识符到实际地址页标识符的第二转换，其中处理上下文切换将仅使每个条目的一部分无效，从而减少与上下文切换相关联的未命中。

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