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    • 2. 发明授权
      US5829033A Optimizing responses in a coherent distributed electronic system including a computer system 失效
    • Optimizing responses in a coherent distributed electronic system including a computer system
    • 在包括计算机系统的连贯分布式电子系统中优化响应
    • US5829033A
    • 1998-10-27
    • US673059
    • 1996-07-01
    • Erik Hagersten , Ashok Singhal , Bjorn Liencres
    • Erik Hagersten , Ashok Singhal , Bjorn Liencres
    • G06F12/08 , G06F13/368 , G06F13/00
    • G06F13/368 , G06F12/0831
    • In a computer system implementing state transitions that change logically and atomically at an address packet independently of a response, the coherence domain is extended among distributed memory. As such, memory line ownership transfers upon request, and not upon requestor receipt of data. Requestor receipt of data is rapidly implemented by providing a ReadToShareFork transaction that simultaneously causes a write-type operation that updates invalid data from a requested memory address, and provides the updated data to the requesting device. More specifically, when writing valid data to memory, the ReadToShare Fork transaction simultaneously causes reissuance of the originally requested transaction using the same memory address and ID information. The requesting device upon recognizing its transaction ID on the bus system will pull the now valid data from the desired memory location.
    • 在实现状态转换的计算机系统中，其独立于响应在地址分组上逻辑地和原子地地改变，所述相干域在分布式存储器之间被扩展。 因此，内存线所有权根据请求转移，而不是请求者接收数据。 通过提供ReadToShareFork事务来快速实现数据的请求者接收，该事务同时导致从所请求的存储器地址更新无效数据的写入型操作，并将更新的数据提供给请求设备。 更具体地说，当向存储器写入有效数据时，ReadToShare Fork事务同时使用相同的存储器地址和ID信息来重新发出原始请求的事务。 请求设备在总线系统上识别其交易ID将从期望的存储器位置提​​取现在的有效数据。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 3. 发明授权
      US5287362A Mechanism for implementing multiple time-outs 失效
    • Mechanism for implementing multiple time-outs
    • 实施多次超时的机制
    • US5287362A
    • 1994-02-15
    • US885120
    • 1992-05-18
    • Bjorn Liencres
    • Bjorn Liencres
    • G06F11/30 , G06F11/00 , H03K21/00
    • G06F11/0757
    • A time-out detector for a computer system to record any number of time-out events with a predetermined period. The time-out detector comprises A-counter coupled to a transmission medium for incrementing in response to an initiating event and decrementing in response to a terminating event; B-counter coupled to the transmission medium for incrementing in response to an initiating event and decrementing in response to a terminating event; I-state bit coupled to the A- and B- counters for toggling between logic 0 and logic 1 states at each prescale pulse, wherein the logic 0 state causes the A-counter to increment by 1 count at each initiating event, and the logic 1 state causes the B-counter to increment by 1 count at each initiating event; T-state bit coupled to the A- and B- counters for toggling between logic 0 and logic 1 states, wherein the logic 0 state causes the A-counter to decrement by 1 at each terminating event, and if the contents of said A-counter is then equal to 0, the T-state bit is set to 1. The logic 1 state causes the B-counter to decrement by 1 at each terminating event, and if the contents of said B-counter is then equal to 0, the T-state bit is reset to 0, such that the A-counter records any number of time-out events when the I-state bit is logic 1 and the B-counter records any number of time-out events when the I-state bit is logic 0.
    • 一种用于计算机系统的超时检测器，用于以预定周期记录任何数量的超时事件。 超时检测器包括耦合到传输介质的A计数器，用于响应于启动事件递增并响应于终止事件而递减; B计数器耦合到传输介质，用于响应于启动事件递增，并响应终止事件递减; 在每个预分频脉冲下，耦合到A和B计数器的I状态位用于在逻辑0和逻辑1之间切换状态，其中逻辑0状态使得A计数器在每个启动事件处递增1个计数，并且逻辑 1状态使B计数器在每次启动事件时增加1个计数; T状态位耦合到A-和B-计数器，用于在逻辑0和逻辑1状态之间切换，其中逻辑0状态导致A-计数器在每个终止事件时递减1，并且如果所述A- 计数器然后等于0，T状态位设置为1.逻辑1状态导致B计数器在每个终止事件时减1，如果所述B计数器的内容等于0， T状态位复位为0，使得当I状态位为逻辑1时，A计数器记录任何数量的超时事件，并且B计数器记录任何数量的超时事件，当I- 状态位为逻辑0。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US5978874A Implementing snooping on a split-transaction computer system bus 失效
    • Implementing snooping on a split-transaction computer system bus
    • 在分割事务计算机系统总线上实现窥探
    • US5978874A
    • 1999-11-02
    • US673038
    • 1996-07-01
    • Ashok Singhal , Bjorn Liencres , Jeff Price , Frederick M. Cerauskis , David Broniarczyk , Gerald Cheung , Erik Hagersten , Nalini Agarwal
    • Ashok Singhal , Bjorn Liencres , Jeff Price , Frederick M. Cerauskis , David Broniarczyk , Gerald Cheung , Erik Hagersten , Nalini Agarwal
    • G06F12/08 , G06F13/368 , G06F13/00
    • G06F13/368 , G06F12/0831
    • Snooping is implemented on a split transaction snooping bus for a computer system having one or many such buses. Circuit boards including CPU or other devices and/or distributed memory, data input/output buffers, queues including request tag queues, coherent input queues ("CIQ"), and address controller implementing address bus arbitration plug-into one or more split transaction snooping bus systems. All devices snoop on the address bus to learn whether an identified line is owned or shared, and an appropriate owned/shared signal is issued. Receipt of an ignore signal blocks CIQ loading of a transaction until the transaction is reloaded and ignore is deasserted. Ownership of a requested memory line transfers immediately at time of request. Asserted requests are queued such that state transactions on the address bus occur atomically logically without dependence upon the request. Subsequent requests for the same data are tagged to become the responsibility of the owner-requestor. A subsequent requestor's activities are not halted awaiting grant and completion of an earlier request transaction. Processor-level cache changes state upon receipt of transaction data. A single multiplexed arbitration bus carries address bus and data bus request transactions, which transactions are each two-cycles in length.
    • 在具有一个或多个这样的总线的计算机系统的分离事务监听总线上实现侦听。 电路板包括CPU或其他设备和/或分布式存储器，数据输入/输出缓冲器，包括请求标签队列，相干输入队列（“CIQ”）和地址控制器的队列，实现地址总线仲裁插入到一个或多个拆分事务监听 总线系统 所有设备在地址总线上窥探，了解所标识的行是否拥有或共享，并发出适当的拥有/共享信号。 接收忽略信号阻止事务的CIQ加载，直到重新加载事务并忽略忽略。 所请求的内存线的所有权在请求时立即转移。 被排除的请求排队，使得地址总线上的状态事务在逻辑上发生，而不依赖于请求。 对相同数据的后续请求被标记为成为所有者请求者的责任。 后续请求者的活动不会暂停等待授予并完成较早的请求事务。 处理器级缓存在收到交易数据后更改状态。 单个复用仲裁总线承载地址总线和数据总线请求事务，这些事务的长度分别为两个周期。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US5911052A Split transaction snooping bus protocol 失效
    • Split transaction snooping bus protocol
    • 拆分事务侦听总线协议
    • US5911052A
    • 1999-06-08
    • US673967
    • 1996-07-01
    • Ashok Singhal , Bjorn Liencres , Jeff Price , Frederick M. Cerauskis , David Broniarczyk , Gerald Cheung , Erik Hagersten , Nalini Agarwal
    • Ashok Singhal , Bjorn Liencres , Jeff Price , Frederick M. Cerauskis , David Broniarczyk , Gerald Cheung , Erik Hagersten , Nalini Agarwal
    • G06F12/08 , G06F13/368 , G06F13/00
    • G06F13/368 , G06F12/0831
    • A split transaction snooping bus protocol and architecture is provided for use in a system having one or many such buses. Circuit boards including CPU or other devices and/or distributed memory, data input/output buffers, queues including request tag queues, coherent input queues ("CIQ"), and address controller implementing address bus arbitration plug-into one or more split transaction snooping bus systems. All devices snoop on the address bus to learn whether an identified line is owned or shared, and an appropriate owned/shared signal is issued. Receipt of an ignore signal blocks CIQ loading of a transaction until the transaction is reloaded and ignore is deasserted. Ownership of a requested memory line transfers immediately at time of request. Asserted requests are queued such that state transactions on the address bus occur atomically logically without dependence upon the request. Subsequent requests for the same data are tagged to become the responsibility of the owner-requestor. A subsequent requestor's activities are not halted awaiting grant and completion of an earlier request transaction. Processor-level cache changes state upon receipt of transaction data. A single multiplexed arbitration bus carries address bus and data bus request transactions, which transactions are each two-cycles in length.
    • 分组交易监听总线协议和架构被提供用于具有一个或多个这样的总线的系统中。 电路板包括CPU或其他设备和/或分布式存储器，数据输入/输出缓冲器，包括请求标签队列，相干输入队列（“CIQ”）和地址控制器的队列，实现地址总线仲裁插入到一个或多个拆分事务监听 总线系统 所有设备在地址总线上窥探，了解所标识的行是否拥有或共享，并发出适当的拥有/共享信号。 接收忽略信号阻止事务的CIQ加载，直到重新加载事务并忽略忽略。 所请求的内存线的所有权在请求时立即转移。 被排除的请求排队，使得地址总线上的状态事务在逻辑上发生，而不依赖于请求。 对相同数据的后续请求被标记为成为所有者请求者的责任。 后续请求者的活动不会暂停等待授予并完成较早的请求事务。 处理器级缓存在收到交易数据后更改状态。 单个复用仲裁总线承载地址总线和数据总线请求事务，这些事务的长度分别为两个周期。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US5497470A Method and apparatus for providing a high through put cache tag controller 失效
    • Method and apparatus for providing a high through put cache tag controller
    • 用于提供高通过缓存标签控制器的方法和装置
    • US5497470A
    • 1996-03-05
    • US885118
    • 1992-05-18
    • Bjorn Liencres
    • Bjorn Liencres
    • G06F12/08 , G06F13/14
    • G06F12/0855
    • A cache tag controller for a cache tag memory for receiving multiple consecutive cache tag modify operations through a system bus to update cache tags in the cache tag memory. The cache tag controller comprises memory for storing cache tags; address register coupled to the memory for specifying a cache tag in the memory, the address register receiving a first modify operation from a system bus; read register coupled to the memory for reading the cache tag according to the address; first update circuit coupled to the read register for modifying the cache tag based on the first modify operation; stage register coupled to the first update circuit for storing an updated cache tag outputted from the first update circuit in response to the first modify operation; compare circuit coupled to the system bus for determining whether a second modify operation from the system bus is for the same cache tag in the memory as the first modify operation, the second modify operation being transmitted from said system bus before the first modify operation completes writing to the memory; second update circuit coupled to the stage register and compare circuit for modifying the updated cache tag in the stage register means according to the second modify operation if the modify operation is for the same cache tag as the first modify operation; and write register coupled to the memory for writing the first and second updated cache tags to the memory means as specified by the address from the address register.
    • 用于缓存标签存储器的缓存标签控制器，用于通过系统总线接收多个连续的高速缓存标签修改操作，以更新高速缓存标签存储器中的高速缓存标签。 高速缓存标签控制器包括用于存储高速缓存标签的存储器; 地址寄存器，用于在存储器中指定高速缓存标签，所述地址寄存器从系统总线接收第一修改操作; 读寄存器耦合到存储器，用于根据地址读缓存标签; 第一更新电路，耦合到所述读寄存器，用于基于所述第一修改操作修改所述高速缓存标签; 所述第一更新电路响应于所述第一修改操作，存储从所述第一更新电路输出的更新的高速缓存标签; 耦合到系统总线的比较电路，用于确定来自系统总线的第二修改操作是否用于与第一修改操作相同的存储器中的高速缓存标签，在第一修改操作完成写入之前，从所述系统总线发送第二修改操作 到记忆中 如果所述修改操作是针对与所述第一修改操作相同的高速缓存标签，则根据所述第二修改操作，耦合到所述级寄存器和比较电路的第二更新电路，用于修改所述级寄存器装置中的更新的高速缓存标签; 以及耦合到存储器的写寄存器，用于将第一和第二更新的高速缓存标签写入由地址寄存器中的地址指定的存储器装置。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 7. 发明授权
      US5644731A Method and apparatus for hot plugging/unplugging a sub-system to an electrically powered system 失效
    • Method and apparatus for hot plugging/unplugging a sub-system to an electrically powered system
    • 将子系统热插拔插入电力系统的方法和装置
    • US5644731A
    • 1997-07-01
    • US499150
    • 1995-07-07
    • Bjorn Liencres , Ashok Singhal , Jeff Price , Kang S. Lim
    • Bjorn Liencres , Ashok Singhal , Jeff Price , Kang S. Lim
    • G06F1/26 , G06F1/18 , G06F3/00 , G06F13/40 , G08B21/00 , H02J1/14 , G06F13/20
    • H02J1/14 , G06F13/4081
    • The present invention provides an "alert" interface for a component which can be safely "hot-plugged/unplugged" to an "alert" interconnect of an electrically powered system. The alert interface has a mating edge which includes daughter precharge/ground connectors, a daughter (engage) waning connector, a number of daughter signal connectors and a daughter engage connector. The alert interconnect includes corresponding mother connectors. The respective connectors of the interconnect and the interface are arranged so that they mate in the following exemplary order when the interface is hot-plugged/unplugged to the interconnect: precharge/ground connectors, warning connectors, signal connectors and finally engage connectors. When the daughter (engage) warning connector mates with the mother warning connector, the component sends an "engage warning" signal to the powered system. Eventully, all the signal connectors mate followed by the engage connectors, enabling the component to send an "engaged" signal to the system indicating that all the signal connectors have completely mated. In accordance with another aspect of the invention, the component can also be safely "hot-unplugged" by first, substantially increasing the degree of recess of the daughter engage connector relative to the daughter signal connectors along the mating edge, and second, doubling the daughter engage connector to function as a daughter disengage warning connector.
    • 本发明提供了一种用于组件的“警报”界面，该组件可以安全地“热插拔”到电力系统的“警报”互连。 警报界面具有配合边缘，其包括女儿预充电/接地连接器，女儿（接合）连接器，多个子信号连接器和女儿接合连接器。 警报互连包括相应的母连接器。 互连和接口的相应连接器被布置成当接口被热插拔插入到互连：预充电/接地连接器，警告连接器，信号连接器并且最终接合连接器时，它们以下列示例顺序配合。 当女儿（接合）警告连接器与母体警告连接器配合时，组件向动力系统发送“接合警告”信号。 Eventully，所有的信号连接器都配合接合连接器，使组件能够向系统发送一个“已接合”信号，表明所有的信号连接器已完全配合。 根据本发明的另一方面，该部件还可以首先安全地“热插拔”，从而基本上增加了女孩接合连接器相对于沿着配合边缘的子信号连接器的凹陷度，其次，将 女儿接合连接器作为女儿脱开警告连接器。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 9. 发明授权
      US5434993A Methods and apparatus for creating a pending write-back controller for a cache controller on a packet switched memory bus employing dual directories 失效
    • Methods and apparatus for creating a pending write-back controller for a cache controller on a packet switched memory bus employing dual directories
    • 用于在采用双目录的分组交换存储器总线上为高速缓存控制器创建待决回写控制器的方法和装置
    • US5434993A
    • 1995-07-18
    • US973309
    • 1992-11-09
    • Bjorn Liencres , Douglas Lee , Pradeep S. Sindhu , Tung Pham
    • Bjorn Liencres , Douglas Lee , Pradeep S. Sindhu , Tung Pham
    • G06F12/08
    • G06F12/0804 , G06F12/0831
    • A write-back cache control system having a pending write-back cache controller in a multiprocessor cache memory structure. The processor subsystems in the multiprocessor system are coupled together using a high-speed synchronous packet switching bus called a memory bus. Each processor subsystem has an associated cache control system. When a processor's cache control system does not have a required memory location in the cache memory, it broadcasts a memory request packet across the memory bus for the required data. If an owned cache line is being replaced, the cache control system copies the old cache line data to the pending write-back cache controller which is responsible for the write-backs of owned cache lines to main memory. The cache control system then transfers ownership of the old replaced cache line to the pending write-back controller. When the cache control system receives the new cache line information from the memory bus, it immediately replaces the cache line and allows the processing to continue. By buffering the old cache line in the pending write-back controller, the cache control system allows the new cache line to be requested before the old cache line is written back to main memory thereby reducing the cache line replacement latency period.
    • 一种回写式高速缓存控制系统，其具有多处理器高速缓冲存储器结构中的等待写回高速缓存控制器。 多处理器系统中的处理器子系统使用称为存储器总线的高速同步分组交换总线耦合在一起。 每个处理器子系统具有相关联的高速缓存控制系统。 当处理器的缓存控制系统在高速缓冲存储器中没有所需的存储器位置时，它通过存储器总线广播存储器请求数据包以获得所需的数据。 如果所有的高速缓存行被替换，则高速缓存控制系统将旧的高速缓存行数据复制到等待写回高速缓存控制器，该控制器负责将所有的高速缓存行写回到主存储器。 然后，高速缓存控制系统将旧的替换的高速缓存行的所有权转移到等待写回控制器。 当高速缓存控制系统从存储器总线接收到新的高速缓存线信息时，它立即替换高速缓存线并允许处理继续。 通过缓冲未完成的回写控制器中的旧高速缓存行，高速缓存控制系统允许在将旧的高速缓存行写回到主存储器之前请求新的高速缓存行，从而减少高速缓存行替换等待时间。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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