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1. 发明申请

US20090096539A1 Error Protection Method, TDC module, CTDC Module, All-Digital Phase-Locked Loop, and Calibration Method thereof 有权
标题翻译：错误保护方法，TDC模块，CTDC模块，全数字锁相环及其校准方法
公开(公告)号：US20090096539A1
公开(公告)日：2009-04-16
申请号：US12235624
申请日：2008-09-23
申请人： Hsiang-Hui Chang , Bing-Yu Hsieh , Jing-Hong Conan Zhan
发明人： Hsiang-Hui Chang , Bing-Yu Hsieh , Jing-Hong Conan Zhan
IPC分类号： H03L7/085 , H03M13/00
CPC分类号： H03L7/085 , H03L7/0991 , H03L2207/50
摘要： An error predict code is added into a cycle signal for raising precision of an output signal of a time-to-digital (TDC) decoder. A cyclic TDC (CTDC) is specifically designed within a phase-frequency detector (PFD)/CTDC module of an all-digital phase-locked loop (ADPLL) for enhancing loop bandwidth calibration of the ADPLL. A calibration method is used on the PFD/CTDC module for enhancing the loop bandwidth calibration of the ADPLL as well.
摘要翻译：错误预测码被添加到周期信号中，以提高时间数字（TDC）解码器的输出信号的精度。在全数字锁相环（ADPLL）的相位频率检测器（PFD）/ CTDC模块中专门设计了循环TDC（CTDC），用于增强ADPLL的环路带宽校准。在PFD / CTDC模块上使用校准方法，以增强ADPLL的环路带宽校准。

2. 发明申请

US20090096538A1 ALL-DIGITAL PHASE-LOCKED LOOP, LOOP BANDWIDTH CALIBRATION METHOD, AND LOOP GAIN CALIBRATION METHOD FOR THE SAME 有权
标题翻译：全数字锁相环路，环路带宽校准方法及其环路增益校准方法
公开(公告)号：US20090096538A1
公开(公告)日：2009-04-16
申请号：US12235615
申请日：2008-09-23
申请人： Hsiang-Hui Chang , Ping-Ying Wang , Jing-Hong Conan Zhan , Bing-Yu Hsieh
发明人： Hsiang-Hui Chang , Ping-Ying Wang , Jing-Hong Conan Zhan , Bing-Yu Hsieh
IPC分类号： H03L7/08
CPC分类号： H03L7/085 , H03L7/0991 , H03L2207/50
摘要： For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.
摘要翻译：为了减少模拟锁相环中的误差，使用具有数字组件和数字操作的全数字锁相环（ADPLL）。 ADPLL也可用于直接调频（DFM）。通过将ADPLL的比例路径增益定义为ADPLL的带宽和参考频率，通过TDC增益，DCO增益，分频器的分频比，放大器的增益或其组合，增益可以调整放大器，使得可以良好校准ADPLL的最佳环路带宽。为了达到ADPLL完全数字化的目的，TDC和DCO的收益可能会以数字方式进一步调整。

3. 发明申请

US20070280072A1 APPARATUS FOR DEMODULATING ADDRESS IN PRE-GROOVE SYMBOLS AND APPARATUS FOR DECODING PRE-PIT SYMBOLS 失效
标题翻译：用于解除预编码符号的地址的装置和解码前缀符号的装置
公开(公告)号：US20070280072A1
公开(公告)日：2007-12-06
申请号：US11755237
申请日：2007-05-30
申请人： Bing-Yu Hsieh , Yuh Cheng , Shu-Hung Chou , Jung-Feng Ho
发明人： Bing-Yu Hsieh , Yuh Cheng , Shu-Hung Chou , Jung-Feng Ho
IPC分类号： G11B20/10
CPC分类号： G11B20/1419 , G11B27/24 , G11B2020/1269
摘要： The invention provides an apparatus for demodulating an Address In Pre-groove (ADIP) symbol. The ADIP symbol is carried by a wobble signal of an optical disk and comprises a series of ADIP bits permuted according to one of a plurality of permutation patterns to make up the ADIP symbol. A wobble extraction module extracts the wobble signal from the optical disk. A reference wobble generator generates a reference wobble with the same frequency and phase as a fundamental frequency and phase of a positive wobble cycle of the wobble signal. A waveform difference measurement module then measures a difference between the wobble signal and the reference wobble to obtain a series of difference measurement values respectively corresponding to the ADIP bits. A pattern matching module then compares probabilities of the permutation of the ADIP bits agreeing with each of the permutation patterns according to the difference measurement values to determine the ADIP symbol.
摘要翻译：本发明提供了一种用于解调预编码地址（ADIP）符号的装置。 ADIP符号由光盘的摆动信号承载，并且包括根据多个置换模式中的一个置换的一系列ADIP位，以构成ADIP符号。摆动提取模块从光盘中提取摆动信号。参考摆动发生器产生与摆动信号的正摆动周期的基频和相位相同的频率和相位的参考摆动。波形差测量模块然后测量摆动信号和参考摆动之间的差异，以获得分别对应于ADIP位的一系列差分测量值。模式匹配模块然后根据差值测量值来比较与每个置换模式一致的ADIP位置的概率，以确定ADIP符号。

4. 发明申请

US20070279274A1 AUTOMATIC POWER CONTROL SYSTEM FOR OPTICAL DISC DRIVE AND METHOD THEREOF 失效
标题翻译：光盘驱动自动功率控制系统及其方法
公开(公告)号：US20070279274A1
公开(公告)日：2007-12-06
申请号：US11758119
申请日：2007-06-05
申请人： Bing-Yu Hsieh , Ming-Jiou Yu , Kuo-Jung Lan , Shu-Hung Chou , Chih-Ching Chen , Chia-Wei Liao
发明人： Bing-Yu Hsieh , Ming-Jiou Yu , Kuo-Jung Lan , Shu-Hung Chou , Chih-Ching Chen , Chia-Wei Liao
IPC分类号： H03M1/12
CPC分类号： H03M1/1225 , G11B7/0903 , G11B7/0912 , G11B7/0941 , G11B7/1263 , H03M1/129
摘要： An automatic power control system, a down sampling circuit and a down sampling method. The automatic power control system is incorporated in an optical disc drive comprising a laser diode for receiving a control signal to generate a laser beam; and a photodetector for detecting the laser beam to generate an analog input signal. The automatic power control system comprises an analog-to-digital converter, a down sampling circuit, a comparator, and a digital-to-analog converter. The analog-to-digital converter converts the analog input signal to digital data. The down sampling circuit, coupled to the analog-to-digital converter, comprises a down sampler, a counter, and a controller. The down sampler receives a predetermined amount of digital data to generate representation data. The counter, coupled to the down sampler, calculates the amount of digital data, and resets the down sampler when the amount equals or exceeds the predetermined count. The controller, coupled to the counter, disables the counter when the digital data is invalid. The comparator, coupled to the down sampling circuit, compares the representation data with predetermined target data to generate error data. The digital-to-analog converter, coupled to the comparator, converts the error data to analog to generate the control signal.
摘要翻译：自动功率控制系统，下采样电路和下采样方法。自动功率控制系统结合在包括用于接收控制信号以产生激光束的激光二极管的光盘驱动器中; 以及用于检测激光束以产生模拟输入信号的光电检测器。自动功率控制系统包括模数转换器，下采样电路，比较器和数 - 模转换器。模数转换器将模拟输入信号转换为数字数据。耦合到模数转换器的下采样电路包括下采样器，计数器和控制器。下采样器接收预定量的数字数据以产生表示数据。耦合到下采样器的计数器计算数字数据量，并且当量等于或超过预定计数时重置下采样器。耦合到计数器的控制器在数字数据无效时禁用计数器。耦合到下采样电路的比较器将表示数据与预定目标数据进行比较以产生误差数据。耦合到比较器的数模转换器将误差数据转换成模拟以产生控制信号。

5. 发明申请

US20070164823A1 Automatic gain control apparatus 有权
标题翻译：自动增益控制装置
公开(公告)号：US20070164823A1
公开(公告)日：2007-07-19
申请号：US11334405
申请日：2006-01-19
申请人： Bing-Yu Hsieh , Meng-Hsueh Lin , Wei-Hsuan Tu
发明人： Bing-Yu Hsieh , Meng-Hsueh Lin , Wei-Hsuan Tu
IPC分类号： H03G3/10
CPC分类号： H03G3/001 , H03M1/185
摘要： An automatic gain control apparatus receiving an analog signal and outputting a digital signal includes a variable gain amplifier, an A/D converter, and a feedback circuit. The variable gain amplifier amplifies the analog signal with a gain. The A/D converter converts the amplified analog signal to the digital signal. The feedback circuit includes an amplitude level detector, a range detector, and a gain controller. The amplitude level detector generates a first amplitude level and a second amplitude level in response to the digital signal. The range detector generates an adjustment signal in response to the first amplitude level and the second amplitude level. The gain controller adjusts a gain control level for the variable gain amplifier in response to the adjustment signal.
摘要翻译：接收模拟信号并输出数字信号的自动增益控制装置包括可变增益放大器，A / D转换器和反馈电路。可变增益放大器以增益放大模拟信号。 A / D转换器将放大的模拟信号转换为数字信号。反馈电路包括幅度电平检测器，量程检测器和增益控制器。振幅电平检测器响应于数字信号产生第一幅度电平和第二幅度电平。范围检测器响应于第一幅度电平和第二幅度电平产生调整信号。增益控制器响应于调节信号调整可变增益放大器的增益控制电平。

6. 发明授权

US08395453B2 Error compensation method, digital phase error cancellation module, and ADPLL thereof 失效
标题翻译：误差补偿方法，数字相位误差消除模块及其ADPLL
公开(公告)号：US08395453B2
公开(公告)日：2013-03-12
申请号：US12235623
申请日：2008-09-23
申请人： Hsiang-Hui Chang , Bing-Yu Hsieh , Jing-Hong Conan Zhan
发明人： Hsiang-Hui Chang , Bing-Yu Hsieh , Jing-Hong Conan Zhan
IPC分类号： H03L7/08 , H03C3/06
CPC分类号： H03L7/085 , H03L7/0991 , H03L2207/50
摘要： Phase error of a time-to-digital converter (TDC) within an all-digital phase-locked loop (ADPLL) is compensated by predicting possible phase error, which are predicted according to an estimated quantization error, a period of a digital-controlled oscillator (DCO), a gain of the TDC or a combination thereof. By appropriate inductions, the possible phase error may be further indicated by the quantization error, a code variance corresponding to a half of a reference period received by a TDC module having the TDC, a dividing ratio of a frequency divider of the ADPLL, a fractional number related to the quantization error or a combination thereof. A digital phase error cancellation module is also used for generating the possible phase error for compensating the phase error of the TDC.
摘要翻译：通过预测根据估计的量化误差预测的可能的相位误差来补偿全数字锁相环（ADPLL）内的时间 - 数字转换器（TDC）的相位误差，数字控制振荡器（DCO），TDC的增益或其组合。通过适当的导入，可能的相位误差可以由量化误差进一步指示，对应于具有TDC的TDC模块接收的参考周期的一半的代码方差，ADPLL的分频器的分频比，分数与量化误差相关的数字或其组合。数字相位误差消除模块还用于产生用于补偿TDC的相位误差的可能的相位误差。

7. 发明授权

US08228128B2 All-digital phase-locked loop, loop bandwidth calibration method, and loop gain calibration method for the same 有权
标题翻译：全数字锁相环，环路带宽校准方法和环路增益校准方法相同
公开(公告)号：US08228128B2
公开(公告)日：2012-07-24
申请号：US12838502
申请日：2010-07-19
申请人： Hsiang-Hui Chang , Ping-Ying Wang , Jing-Hong Conan Zhan , Bing-Yu Hsieh
发明人： Hsiang-Hui Chang , Ping-Ying Wang , Jing-Hong Conan Zhan , Bing-Yu Hsieh
IPC分类号： H03L7/085
CPC分类号： H03L7/085 , H03L7/0991 , H03L2207/50
摘要： For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.
摘要翻译：为了减少模拟锁相环中的误差，使用具有数字组件和数字操作的全数字锁相环（ADPLL）。 ADPLL也可用于直接调频（DFM）。通过将ADPLL的比例路径增益定义为ADPLL的带宽和参考频率，通过TDC增益，DCO增益，分频器的分频比，放大器的增益或其组合，增益可以调整放大器，使得可以良好校准ADPLL的最佳环路带宽。为了达到ADPLL完全数字化的目的，TDC和DCO的收益可能会以数字方式进一步调整。

8. 发明授权

US08149146B2 Automatic power control system for optical disc drive and method thereof 有权
标题翻译：用于光盘驱动器的自动功率控制系统及其方法
公开(公告)号：US08149146B2
公开(公告)日：2012-04-03
申请号：US13008485
申请日：2011-01-18
申请人： Bing-Yu Hsieh , Ming-Jiou Yu , Kuo-Jung Lan , Shu-Hung Chou , Chih-Ching Chen , Chia-Wei Liao
发明人： Bing-Yu Hsieh , Ming-Jiou Yu , Kuo-Jung Lan , Shu-Hung Chou , Chih-Ching Chen , Chia-Wei Liao
IPC分类号： H03M7/00
CPC分类号： H03M1/1225 , G11B7/0903 , G11B7/0912 , G11B7/0941 , G11B7/1263 , H03M1/129
摘要： An automatic power control system, an automatic power control method, a down sampling circuit and a down sampling method. The automatic power control system is incorporated in an optical disc drive comprising a laser diode for receiving a control signal to generate a laser beam; and a photodetector for detecting the laser beam to generate an analog input signal. The automatic power control system comprises an analog-to-digital converter, a down sampling circuit, a comparator, and a digital-to-analog converter. The analog-to-digital converter converts the analog input signal to digital data. The down sampling circuit, coupled to the analog-to-digital converter, comprises a down sampler, a counter, and a controller. The down sampler receives a predetermined amount of digital data to generate representation data. The counter, coupled to the down sampler, calculates the amount of digital data, and resets the down sampler when the amount equals or exceeds the predetermined count. The controller, coupled to the counter, disables the counter when the digital data is invalid. The comparator, coupled to the down sampling circuit, compares the representation data with predetermined target data to generate error data. The digital-to-analog converter, coupled to the comparator, converts the error data to analog to generate the control signal.
摘要翻译：自动功率控制系统，自动功率控制方法，下采样电路和下采样方法。自动功率控制系统结合在包括用于接收控制信号以产生激光束的激光二极管的光盘驱动器中; 以及用于检测激光束以产生模拟输入信号的光电检测器。自动功率控制系统包括模数转换器，下采样电路，比较器和数 - 模转换器。模数转换器将模拟输入信号转换为数字数据。耦合到模数转换器的下采样电路包括下采样器，计数器和控制器。下采样器接收预定量的数字数据以产生表示数据。耦合到下采样器的计数器计算数字数据量，并且当量等于或超过预定计数时重置下采样器。耦合到计数器的控制器在数字数据无效时禁用计数器。耦合到下采样电路的比较器将表示数据与预定目标数据进行比较以产生误差数据。耦合到比较器的数模转换器将误差数据转换成模拟以产生控制信号。

9. 发明授权

US08031008B2 PLL with loop bandwidth calibration circuit 有权
标题翻译： PLL带环路带宽校准电路
公开(公告)号：US08031008B2
公开(公告)日：2011-10-04
申请号：US12426981
申请日：2009-04-21
申请人： Ping-Ying Wang , Bing-Yu Hsieh , Ling-Wei Ke , Tai Yuan Yu
发明人： Ping-Ying Wang , Bing-Yu Hsieh , Ling-Wei Ke , Tai Yuan Yu
IPC分类号： H03L7/00
CPC分类号： H03L7/1976 , H03L7/087 , H03L7/093 , H03L7/099
摘要： A phase locked loop (PLL) with a loop bandwidth calibration circuit is provided. The mixed-mode PLL comprises an analog phase correction path, a digital frequency correction path, a calibration current source, and a loop bandwidth calibration circuit. The analog phase correction path comprises a linear phase correction unit (LPCU). The digital frequency correction path comprises a digital integral path circuit. The calibration current source is coupled to the LPCU. The loop bandwidth calibration circuit is coupled to a frequency divider and coupled between the input and output of the PLL. The loop bandwidth calibration circuit operates after the calibration current source injects a calibration current into the LPCU.
摘要翻译：提供了带有环路带宽校准电路的锁相环（PLL）。混合模式PLL包括模拟相位校正路径，数字频率校正路径，校准电流源和环路带宽校准电路。模拟相位校正路径包括线性相位校正单元（LPCU）。数字频率校正路径包括数字积分路径电路。校准电流源耦合到LPCU。环路带宽校准电路耦合到分频器并耦合在PLL的输入和输出之间。循环带宽校准电路在校准电流源将校准电流注入LPCU之后运行。

10. 发明申请

US20110122747A1 Automatic Power Control System for Optical Disc Drive and Method Thereof 有权
标题翻译：光盘驱动自动电源控制系统及其方法
公开(公告)号：US20110122747A1
公开(公告)日：2011-05-26
申请号：US13008485
申请日：2011-01-18
申请人： Bing-Yu Hsieh , Ming-Jiou Yu , Kuo-Jung Lan , Shu-Hung Chou , Chih-Ching Chen , Chia-Wei Liao
发明人： Bing-Yu Hsieh , Ming-Jiou Yu , Kuo-Jung Lan , Shu-Hung Chou , Chih-Ching Chen , Chia-Wei Liao
IPC分类号： G11B20/10
CPC分类号： H03M1/1225 , G11B7/0903 , G11B7/0912 , G11B7/0941 , G11B7/1263 , H03M1/129
摘要： An automatic power control system, an automatic power control method, a down sampling circuit and a down sampling method. The automatic power control system is incorporated in an optical disc drive comprising a laser diode for receiving a control signal to generate a laser beam; and a photodetector for detecting the laser beam to generate an analog input signal. The automatic power control system comprises an analog-to-digital converter, a down sampling circuit, a comparator, and a digital-to-analog converter. The analog-to-digital converter converts the analog input signal to digital data. The down sampling circuit, coupled to the analog-to-digital converter, comprises a down sampler, a counter, and a controller. The down sampler receives a predetermined amount of digital data to generate representation data. The counter, coupled to the down sampler, calculates the amount of digital data, and resets the down sampler when the amount equals or exceeds the predetermined count. The controller, coupled to the counter, disables the counter when the digital data is invalid. The comparator, coupled to the down sampling circuit, compares the representation data with predetermined target data to generate error data. The digital-to-analog converter, coupled to the comparator, converts the error data to analog to generate the control signal.
摘要翻译：自动功率控制系统，自动功率控制方法，下采样电路和下采样方法。自动功率控制系统结合在包括用于接收控制信号以产生激光束的激光二极管的光盘驱动器中; 以及用于检测激光束以产生模拟输入信号的光电检测器。自动功率控制系统包括模数转换器，下采样电路，比较器和数 - 模转换器。模数转换器将模拟输入信号转换为数字数据。耦合到模数转换器的下采样电路包括下采样器，计数器和控制器。下采样器接收预定量的数字数据以产生表示数据。耦合到下采样器的计数器计算数字数据量，并且当量等于或超过预定计数时重置下采样器。耦合到计数器的控制器在数字数据无效时禁用计数器。耦合到下采样电路的比较器将表示数据与预定目标数据进行比较以产生误差数据。耦合到比较器的数模转换器将误差数据转换成模拟以产生控制信号。

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