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1. 发明授权

US06389525B1 Pattern generator for a packet-based memory tester 有权
标题翻译：用于基于分组的内存测试器的模式生成器
公开(公告)号：US06389525B1
公开(公告)日：2002-05-14
申请号：US09227690
申请日：1999-01-08
申请人： Peter Reichert , Bill Sopkin , Chris Reed
发明人： Peter Reichert , Bill Sopkin , Chris Reed
IPC分类号： G06F1200
CPC分类号： G11C29/56 , G01R31/31813 , G01R31/31926
摘要： A pattern generator for use in a memory tester to provide packet address and data signals to a packet-based memory-under-test is disclosed. The pattern generator includes an address source for generating an external packet memory address signal. The external packet memory address signal represents a plurality of addressable memory elements in the memory-under-test. A plurality of data generators are disposed in parallel relationship and coupled to the output of the address source to receive at least a portion of the packet memory address signal. Each of the data generators has logic operative to derive an internal address from the packet address. The internal address corresponds to an individual memory element within the memory under test. A sequencer is disposed at the outputs of the data generators to distribute the data generator outputs in a packet waveform for application to the memory-under-test.
摘要翻译：公开了一种用于存储器测试器中的模式发生器，用于将分组地址和数据信号提供给基于分组的未被测试的存储器。图案生成器包括用于生成外部分组存储器地址信号的地址源。外部分组存储器地址信号表示被测存储器中的多个可寻址存储器元件。多个数据发生器并行布置并耦合到地址源的输出端以接收分组存储器地址信号的至少一部分。每个数据发生器具有逻辑可操作以从分组地址导出内部地址。内部地址对应于被测存储器内的单独存储元件。定序器设置在数据发生器的输出处，以便将数据发生器输出以分组波形分布以供应用于待测存储器。

2. 发明授权

US06405333B1 Fail array memory control circuit with selective input disable 有权
标题翻译：故障阵列存储器控制电路具有选择性输入禁止
公开(公告)号：US06405333B1
公开(公告)日：2002-06-11
申请号：US09282224
申请日：1999-03-31
申请人： Bill Sopkin
发明人： Bill Sopkin
IPC分类号： G01R3128
CPC分类号： G01R31/3193
摘要： A memory control circuit is disclosed for use in a data path of a failure capture circuit to selectively control the storage of failure information associated with a pin of a device-under-test. The memory control circuit includes a memory controller operative to generate a store signal in response to a failure control signal and a semiconductor memory having a control input coupled to the controller for receiving the store signal. The memory controller operates in response to the store signal to write failure information associated with a particular failure control signal. Disable logic in the memory control circuit is operative according to predetermined conditions for selectively inhibiting the delivery of the failure control signals to the memory controller.
摘要翻译：公开了一种用于故障捕获电路的数据路径中的存储器控制电路，用于选择性地控制与被测器件的引脚相关联的故障信息的存储。存储器控制电路包括可响应于故障控制信号产生存储信号的存储器控制器和具有耦合到控制器的用于接收存储信号的控制输入的半导体存储器。存储器控制器响应于存储信号操作以写入与特定故障控制信号相关联的故障信息。存储器控制电路中的禁止逻辑根据预定条件进行操作，以选择性地禁止将故障控制信号传送到存储器控制器。

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