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1. 发明授权

US07552377B1 Method of and circuit for interleaving data in a data coder 有权
标题翻译：用于在数据编码器中交织数据的方法和电路
公开(公告)号：US07552377B1
公开(公告)日：2009-06-23
申请号：US11055288
申请日：2005-02-10
申请人： Ben J. Jones
发明人： Ben J. Jones
IPC分类号： H03M13/00
CPC分类号： H03M13/256 , H03M13/2764 , H03M13/2771
摘要： According to one aspect of the invention, a method of interleaving data for enabling data coding in a communication network is disclosed, the method including storing parameters required to output address sequences for a matrix, receiving a block size associated with a block of data at a circuit for interleaving data, outputting parameters associated with the stored parameters based upon the block size, and producing an address sequence using the parameters. A circuit for interleaving data for data coding in a communication network is also disclosed. The circuit includes a lookup table storing parameters required to output address sequences for a matrix. A search coupled to the lookup table receives a clock size associated with a matrix and outputs parameters based upon the block size. A computation circuit coupled to receive the parameters outputs an address sequence using the parameters.
摘要翻译：根据本发明的一个方面，公开了一种交织用于在通信网络中实现数据编码的数据的方法，所述方法包括存储输出矩阵输出地址序列所需的参数，接收与一个数据块相关联的块大小用于交织数据的电路，基于块大小输出与存储的参数相关联的参数，以及使用参数产生地址序列。还公开了一种用于在通信网络中交织用于数据编码的数据的电路。该电路包括一个查找表，其存储输出矩阵输出地址序列所需的参数。耦合到查找表的搜索接收与矩阵相关联的时钟大小，并基于块大小输出参数。耦合以接收参数的计算电路使用参数输出地址序列。

2. 发明授权

US08930787B1 Decoder in a device receiving data having an error correction code and a method of decoding data 有权
标题翻译：在接收具有纠错码的数据的装置中的解码器和解码数据的方法
公开(公告)号：US08930787B1
公开(公告)日：2015-01-06
申请号：US13308726
申请日：2011-12-01
申请人： Ben J. Jones , William A. Wilkie
发明人： Ben J. Jones , William A. Wilkie
IPC分类号： H03M13/00
CPC分类号： H03M13/1525 , H03M13/1515 , H03M13/19
摘要： A decoder in a device receiving data having an error correction code is described. The decoder comprises a memory storing program code having instructions including control signals for decoding an error correction code; an address generator coupled to the memory, the address generator updating an address coupled to the memory for generating a next control signal; and a data processing circuit coupled to receive an instruction from the memory and further coupled to receive syndrome data, the data processing circuit generating error correction values. A method for decoding data having an error correction code is also disclosed.
摘要翻译：在接收具有纠错码的数据的设备中的解码器被描述。解码器包括存储程序代码的存储器，其具有包括用于解码纠错码的控制信号的指令; 耦合到存储器的地址发生器，地址发生器更新耦合到存储器的地址，用于产生下一个控制信号; 以及数据处理电路，其被耦合以从所述存储器接收指令并进一步耦合以接收校正子数据，所述数据处理电路产生误差校正值。还公开了一种用于解码具有纠错码的数据的方法。

3. 发明授权

US08145877B2 Address generation for quadratic permutation polynomial interleaving 有权
标题翻译：二次置换多项式交织的地址生成
公开(公告)号：US08145877B2
公开(公告)日：2012-03-27
申请号：US12059731
申请日：2008-03-31
申请人： Ben J. Jones , Colin Stirling
发明人： Ben J. Jones , Colin Stirling
IPC分类号： G06F9/26
CPC分类号： G06F9/3552 , G06F9/345 , G06F9/3455 , H03M13/2739
摘要： For address generation, a block size and a skip value are obtained, and at least one address, at least one increment value, and a step value are initialized. For a count index not in excess of a block size, iteratively performed are: selection of an output address for output from at least one phase responsive to at least the at least one address; first update of the at least one address as being equal to summation of the at least one increment and the at least one address modulo the block size; and second update of the at least one increment as being equal to summation of the at least one increment and the step value modulo the block size. The selection and the first and second updates are iteratively repeated responsive to increments of the count index to output a sequence of addresses.
摘要翻译：对于地址生成，获得块大小和跳过值，并且初始化至少一个地址，至少一个增量值和阶跃值。对于不超过块大小的计数指数，迭代地执行：响应于至少一个地址从至少一个相位输出的输出地址的选择; 所述至少一个地址的第一更新等于所述至少一个增量和所述至少一个地址的所述块大小的模拟总和; 以及所述至少一个增量的第二更新等于所述块大小对所述至少一个增量和所述步长值的和的和。响应于计数指数的增加来反复地重复选择和第一和第二更新以输出地址序列。

4. 发明授权

US07610519B1 Vector generation for codes through symmetry 有权
标题翻译：矢量生成代码通过对称
公开(公告)号：US07610519B1
公开(公告)日：2009-10-27
申请号：US11368128
申请日：2006-03-03
申请人： Jeffrey A. Graham , Ben J. Jones
发明人： Jeffrey A. Graham , Ben J. Jones
IPC分类号： G06F11/00 , G11C29/00 , H03M13/00
CPC分类号： H03M13/2771 , G11C2029/0411 , H03M13/275 , H03M13/276 , H03M13/6572
摘要： Apparatus for vector generation is described. A vector generator is associated with a discrete power series symmetric about at least one term and configured to provide vectors, such as QSvectors for a Turbo Code for example. The vectors are each provided in separate portions as a first portion and a second portion. The second portion of a vector of the vectors is generated from the first portion of the vector using symmetry about the at least one term.
摘要翻译：描述用于矢量生成的装置。矢量发生器与关于至少一个术语对称的离散功率系列相关联，并被配置为提供矢量，例如用于Turbo码的QSvectors。各向量分别设置为第一部分和第二部分。矢量的向量的第二部分使用关于至少一个项的对称性从矢量的第一部分生成。

5. 发明申请

US20090249024A1 Address generation for quadratic permutation polynomial interleaving 有权
标题翻译：二次置换多项式交织的地址生成
公开(公告)号：US20090249024A1
公开(公告)日：2009-10-01
申请号：US12059731
申请日：2008-03-31
申请人： Ben J. Jones , Colin Stirling
发明人： Ben J. Jones , Colin Stirling
IPC分类号： G06F9/26
CPC分类号： G06F9/3552 , G06F9/345 , G06F9/3455 , H03M13/2739
摘要： For address generation, a block size and a skip value are obtained, and at least one address, at least one increment value, and a step value are initialized. For a count index not in excess of a block size, iteratively performed are: selection of an output address for output from at least one phase responsive to at least the at least one address; first update of the at least one address as being equal to summation of the at least one increment and the at least one address modulo the block size; and second update of the at least one increment as being equal to summation of the at least one increment and the step value modulo the block size. The selection and the first and second updates are iteratively repeated responsive to increments of the count index to output a sequence of addresses.
摘要翻译：对于地址生成，获得块大小和跳过值，并且初始化至少一个地址，至少一个增量值和阶跃值。对于不超过块大小的计数指数，迭代地执行：响应于至少一个地址从至少一个相位输出的输出地址的选择; 所述至少一个地址的第一更新等于所述至少一个增量和所述至少一个地址的所述块大小的模拟总和; 以及所述至少一个增量的第二更新等于所述块大小对所述至少一个增量和所述步长值的和的和。响应于计数指数的增加来反复地重复选择和第一和第二更新以输出地址序列。

6. 发明授权

US08869013B1 Circuit enabling and a method of generating a product in a decoder circuit 有权
标题翻译：电路使能和在解码器电路中产生产品的方法
公开(公告)号：US08869013B1
公开(公告)日：2014-10-21
申请号：US13308748
申请日：2011-12-01
申请人： Ben J. Jones
发明人： Ben J. Jones
IPC分类号： H03M13/00 , H03M13/15 , G06F7/72
CPC分类号： H03M13/158 , G06F7/724 , H03M13/1515 , H03M13/153 , H03M13/1585
摘要： A circuit enabling generating a product in a decoder circuit is disclosed. The circuit comprises a first memory element coupled to receive a first error value and a first portion of a second error value; a second memory element coupled to receive the first error value and a second portion of the second error value; and an adder circuit coupled to add an output of the first memory element and an output of the second memory element. The output of the first memory element is generated in response to an address based on the first error value and the first portion of the second error value, and the output of the second memory element is generated in response to an address based on the first error value and the second portion of the second error value. A method for generating a product in a decoder circuit is also disclosed.
摘要翻译：公开了一种能够在解码器电路中产生产品的电路。电路包括耦合以接收第一误差值和第二误差值的第一部分的第一存储器元件; 耦合以接收第一误差值的第二存储器元件和第二误差值的第二部分; 以及加法器电路，被耦合以添加第一存储元件的输出和第二存储元件的输出。响应于基于第一误差值和第二误差值的第一部分的地址而产生第一存储器元件的输出，并且响应于基于第一误差的地址产生第二存储器元件的输出值和第二误差值的第二部分。还公开了一种在解码器电路中产生产品的方法。

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