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1. 发明授权

US5388247A History buffer control to reduce unnecessary allocations in a memory stream buffer 失效
标题翻译：历史缓冲区控制，以减少内存流缓冲区中的不必要的分配
公开(公告)号：US5388247A
公开(公告)日：1995-02-07
申请号：US197376
申请日：1994-02-16
申请人： Paul M. Goodwin , Kurt M. Thaller , Barry A. Maskas
发明人： Paul M. Goodwin , Kurt M. Thaller , Barry A. Maskas
IPC分类号： G06F9/38 , G06F12/02 , G06F11/34
CPC分类号： G06F12/0215 , G06F9/383 , G06F9/3832
摘要： A read buffering system employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system bus is not used in memory accesses used to fill the stream buffer. The system stores addresses used for read requests made by a CPU, and if a next sequential address is then detected in a subsequent read request, this is designated to be a stream (i.e., sequential reads). When a stream is thus detected, data is fetched from DRAM memory for addresses following the sequential address, and this prefetched data is stored in one of the FIFOs. The system also prevents the unnecessary prefetching of data by preventing certain CPU requests from being used to detect streams. A FIFO is selected using a least-recently-used algorithm. When the CPU subsequently makes a read request for data in a FIFO, this data can be returned without making a memory access. By taking advantage of page mode, access to the DRAM memory for the prefetch operations can be transparent to the CPU, resulting in substantial performance improvement if sequential accesses are frequent. The data is stored in the DRAMs with ECC check bits, and error detection and correction (EDC) is performed on the read data downstream of the stream buffer, so the stream buffer is protected by EDC.
摘要翻译：读取缓冲系统使用一组FIFO来保存由计算机取出的多个数据流的顺序读取数据。 FIFO位于存储器控制器中，因此系统总线不用于用于填充流缓冲器的存储器访问。该系统存储用于由CPU进行的读取请求的地址，并且如果随后的读取请求中检测到下一个顺序地址，则将其指定为流（即顺序读取）。当如此检测到流时，数据从DRAM存储器中取出顺序地址之后的地址，并且该预取数据存储在FIFO之一中。该系统还通过防止某些CPU请求被用于检测流来防止数据的不必要的预取。使用最近最少使用的算法选择FIFO。当CPU随后对FIFO中的数据进行读取请求时，可以返回该数据而不进行存储器访问。通过利用页面模式，对于预取操作的DRAM存储器的访问对于CPU是透明的，如果顺序访问是频繁的，则导致显着的性能改善。将数据存储在具有ECC校验位的DRAM中，并且对流缓冲器的下游的读取数据执行错误检测和校正（EDC），因此流缓冲器被EDC保护。

2. 发明授权

US5319766A Duplicate tag store for a processor having primary and backup cache memories in a multiprocessor computer system 失效
标题翻译：在多处理器计算机系统中具有主要和备用高速缓冲存储器的处理器的重复标签存储
公开(公告)号：US5319766A
公开(公告)日：1994-06-07
申请号：US874289
申请日：1992-04-24
申请人： Kurt M. Thaller , Jeffrey A. Metzger , Nitin D. Godiwala , Barry A. Maskas
发明人： Kurt M. Thaller , Jeffrey A. Metzger , Nitin D. Godiwala , Barry A. Maskas
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： A processor apparatus for use in a multiprocessor computer system having a main memory storing a plurality of data items and being coupled to a bus operating according of a SNOOPY protocol. The processor apparatus includes a processor, a primary cache, a backup cache and a bus interface. The backup cache memory a first TAG store comprising a plurality of VALID indicators, one VALID indicator for each of the data items currently contained in the backup cache memory. The primary cache memory includes a second TAG store comprising a plurality of address indicators and a plurality of VALID indicators, one address indicator and one VALID indicator for each of the data items currently contained in the primary cache memory. The interface includes a duplicate TAG store coupled to the primary cache memory, the duplicate TAG store consisting of a copy of the address indicators of the second TAG store. The bus interface is coupled to the processor, the backup cache memory and to the bus. The bus interface operates in accordance with a SNOOPY protocol to monitor transactions on the bus for write transactions affecting data items in the corresponding backup cache memory having set VALID indicators. The bus interface will invalidate or update each VALID data item of the backup cache memory when there is a write transaction affecting data item and assert an invalidate signal for an affected data item indicated by the address indicators of the duplicate TAG store. The invalidate signal causes the VALID indicator in the second TAG store for the affected data item to be cleared.
摘要翻译：一种用于多处理器计算机系统的处理器装置，具有存储多个数据项的主存储器，并且耦合到根据SNOOPY协议操作的总线。处理器装置包括处理器，主缓存，备用高速缓存和总线接口。所述备份高速缓冲存储器包括多个VALID指示符的第一TAG存储器，当前包含在备用高速缓冲存储器中的每个数据项的一个VALID指示符。主缓冲存储器包括第二TAG存储器，其包括多个地址指示符和多个VALID指示符，一个地址指示符和一个VALID指示符，用于当前包含在主缓存存储器中的每个数据项。接口包括耦合到主高速缓存存储器的重复TAG存储器，该重复TAG存储器由第二TAG存储器的地址指示符的副本组成。总线接口耦合到处理器，备用高速缓冲存储器和总线。总线接口根据SNOOPY协议进行操作，以监视总线上的事务，以便影响具有设置的VALID指示符的相应备份高速缓冲存储器中的数据项的写入事务。当存在影响数据项的写事务并且为由重复TAG存储器的地址指示符指示的受影响数据项断言无效信号时，总线接口将使备用高速缓冲存储器的每个VALID数据项无效或更新。无效信号导致第二个TAG存储中的VALID指示符被影响的数据项被清除。

3. 发明授权

US4782486A Self-testing memory 失效
标题翻译：自检记忆
公开(公告)号：US4782486A
公开(公告)日：1988-11-01
申请号：US49812
申请日：1987-05-14
申请人： Jesse B. Lipcon , Barry A. Maskas , David K. Morgan
发明人： Jesse B. Lipcon , Barry A. Maskas , David K. Morgan
IPC分类号： G06F12/16 , G11C29/28 , G01R31/28
CPC分类号： G11C29/28
摘要： A self-testing memory simultaneously writes test patterns into the memory banks of the memory, simultaneously compares the contents of one of the memory banks with the contents of the other of the banks, and records errors when the contents of the one memory bank differ from the contents of the other banks.

4. 发明授权

US5553266A Update vs. invalidate policy for a snoopy bus protocol 失效
标题翻译：侦听总线协议的更新与无效策略
公开(公告)号：US5553266A
公开(公告)日：1996-09-03
申请号：US341281
申请日：1994-11-16
申请人： Jeffrey A. Metzger , Barry A. Maskas
发明人： Jeffrey A. Metzger , Barry A. Maskas
IPC分类号： G06F12/08
CPC分类号： G06F12/0833
摘要： The present invention is directed to a computer apparatus for use in a multiprocessor computer system having a main memory storing a plurality of data items and being coupled to a bus. The bus is operated according to a SNOOPY protocol. The computer apparatus includes a processor and a cache memory coupled to the processor. The cache memory contains a subset of the data items stored in the main memory, for access by the processor and includes a TAG store comprising a plurality of VALID indicators, one VALID indicator for each of the data items currently contained in the cache memory. A bus interface is coupled to the cache memory and is adapted for coupling to the bus. The interface operates according to the SNOOPY protocol to monitor transactions on the bus for write transactions affecting data items of the subset having set VALID indicators and determines the identity of each initiator of a write transaction on the bus affecting a VALID data item of the subset. The interface operates further to invalidate or update each VALID data item of the subset when there is a write transaction affecting the data item. An invalidate operation includes a clearing of the corresponding VALID indicator for the affected data item by the interface and an update operation includes overwriting of the affected data item by the interface from the write transaction on the bus. The operation of the interface to invalidate or update is performed as a function of the identity of the initiator of the write transaction determined by the interface.
摘要翻译：本发明涉及一种用于多处理器计算机系统中的计算机装置，其具有存储多个数据项并且耦合到总线的主存储器。总线根据SNOOPY协议进行操作。计算机装置包括处理器和耦合到处理器的高速缓冲存储器。高速缓存存储器包含存储在主存储器中的数据项的子集，供处理器访问，并且包括一个TAG存储器，其包括多个VALID指示符，一个VALID指示符，用于当前包含在高速缓存存储器中的每个数据项。总线接口耦合到高速缓冲存储器并适于耦合到总线。该接口根据SNOOPY协议操作以监视总线上的事务以影响具有设置的VALID指示符的子集的数据项的写入事务，并且确定总线上写入事务的每个发起者的身份，影响该子集的VALID数据项。当存在影响数据项的写事务时，该接口进一步操作以使子集的每个VALID数据项无效或更新。无效操作包括通过接口清除受影响数据项的相应VALID指示符，并且更新操作包括由总线上的写事务通过接口覆盖受影响的数据项。根据接口确定的写事务的发起者的身份执行无效或更新的接口的操作。

5. 发明授权

US5428764A System for radial clock distribution and skew regulation for synchronous clocking of components of a computing system 失效
标题翻译：用于计算系统组件的同步计时的径向时钟分配和偏斜调节系统
公开(公告)号：US5428764A
公开(公告)日：1995-06-27
申请号：US873923
申请日：1992-04-24
申请人： Barry A. Maskas
发明人： Barry A. Maskas
IPC分类号： G06F1/10 , H03K5/135 , H03K5/14
CPC分类号： G06F1/10
摘要： A radial clock distribution system that converts a standard bus clock signal into two pairs of inverted and non-inverted clocking signals. The two pairs of clocking signals have a lower frequency, have a different phase, and are shifted one clock period apart. The clocking signals are transferred over a first set of signal lines of equal length and impedance to computing systems components that are connected to a synchronous bus. Each component includes at least one clock repeater chip to convert the clocking signals (e.g., change these signals to a 5 volt CMOS level) to a different format. The converted clocking signals are then transferred over a second set of signal lines of equal length and impedance to the gate arrays. The gate arrays includes direct drive circuitry that receives the converted clocking signals and transmits these signals to internal driver circuitry. These signals are transferred over low skew lines. The output of the interval driver circuitry is input to local buffer circuitry that distributes the converted clocking signals to elements of a component for use as clocking signals.
摘要翻译：径向时钟分配系统，将标准总线时钟信号转换成两对反相和非反相时钟信号。两对时钟信号具有较低的频率，具有不同的相位，并且间隔一个时钟周期。时钟信号通过相同长度和阻抗的第一组信号线传送到连接到同步总线的计算系统组件。每个组件包括至少一个时钟转发器芯片，用于将时钟信号（例如，将这些信号改变为5伏CMOS电平）转换成不同的格式。转换的时钟信号然后通过等长和阻抗的第二组信号线传送到门阵列。门阵列包括直接驱动电路，其接收转换的时钟信号并将这些信号发送到内部驱动器电路。这些信号通过低偏移线传输。间隔驱动器电路的输出被输入到本地缓冲器电路，其将转换后的时钟信号分配给组件的元件，以用作时钟信号。

6. 发明授权

US5361267A Scheme for error handling in a computer system 失效
标题翻译：计算机系统中的错误处理方案
公开(公告)号：US5361267A
公开(公告)日：1994-11-01
申请号：US874321
申请日：1992-04-24
申请人： Nitin D. Godiwala , Barry A. Maskas , Kurt M. Thaller , Jeffrey A. Metzger
发明人： Nitin D. Godiwala , Barry A. Maskas , Kurt M. Thaller , Jeffrey A. Metzger
IPC分类号： G06F11/00 , G06F11/10 , H03M13/00
CPC分类号： G06F11/10
摘要： The present invention is directed to a control flow logic device for handling data received from a bus by a bus interface, in response to a bus read transaction, and transferred to a processor. The control flow logic includes an error checker to check data received from the bus for hard errors and parity errors and an ECC generator to generate an ECC for the received data, the ECC being forced to a bad ECC when a hard error is detected by the error checker and to a good ECC in the absence of a hard error. An error signal generator is utilized to generate and transmit an error signal to the processor when there is a hard error or a parity error in the received data and a data mover transmits the received data and the ECC to the processor.
摘要翻译：本发明涉及一种用于响应于总线读取事务处理由总线接口从总线接收的数据并传送到处理器的控制流逻辑设备。控制流程逻辑包括一个错误检查器，用于检查从总线接收的数据是否存在硬错误和奇偶校验错误;以及ECC发生器，用于为接收到的数据生成ECC，当ECC检测到硬错误时，ECC被强制为坏ECC 错误检查器和没有硬错误的良好的ECC。当存在接收到的数据中的硬错误或奇偶校验错误并且数据移动器将接收到的数据和ECC发送到处理器时，使用错误信号发生器来产生并向处理器发送错误信号。

7. 发明授权

US5918029A Bus interface slicing mechanism allowing for a control/data-path slice 失效
标题翻译：总线接口切片机制允许控制/数据路径切片
公开(公告)号：US5918029A
公开(公告)日：1999-06-29
申请号：US999899
申请日：1997-09-08
申请人： Jeffrey A. Metzger , Nitin D. Godiwala , Barry A. Maskas , Kurt M. Thaller , Paul M. Goodwin , Donald W. Smelser , David A. Tatosian
发明人： Jeffrey A. Metzger , Nitin D. Godiwala , Barry A. Maskas , Kurt M. Thaller , Paul M. Goodwin , Donald W. Smelser , David A. Tatosian
IPC分类号： G06F13/40 , G06F13/56
CPC分类号： G06F13/4068
摘要： A bus interface is partitionable into at least two slices. Each slice interfaces a respective subset of data from a computer device to a system bus. Each slice also receives a corresponding subset of control information and a complete set of address information from the computer device. Moreover, each slice may be implemented on a single integrated circuit chip, which thus handles both data and control functions.
摘要翻译：总线接口可分为至少两个切片。每个切片将来自计算机设备的数据的相应子集接口到系统总线。每个切片还从计算机设备接收相应的控制信息子集和一组完整的地址信息。此外，每个片可以在单个集成电路芯片上实现，从而处理数据和控制功能。

8. 发明授权

US5555382A Intelligent snoopy bus arbiter 失效
标题翻译：智能侦测总线仲裁器
公开(公告)号：US5555382A
公开(公告)日：1996-09-10
申请号：US359321
申请日：1994-12-19
申请人： Kurt M. Thaller , Nitin D. Godiwala , Barry A. Maskas
发明人： Kurt M. Thaller , Nitin D. Godiwala , Barry A. Maskas
IPC分类号： G06F12/08 , G06F13/362 , G06F9/26 , H01J13/00
CPC分类号： G06F13/362 , G06F12/0831
摘要： The present invention is directed to a method for arbitrating for control of a bus in a multiprocessor system. The multiprocessor system comprises a plurality of processors and a main memory coupled to one another by the bus, each processor including a cache memory accessible by the corresponding processor and in connection with transactions on the bus. The method includes the steps of generating requests for control of the bus and granting control of the bus in respect of one of the requests. The bus is monitored for preselected transaction activity on the bus; and an idle cycle is inserted on the bus upon monitoring the preselected transaction activity.
摘要翻译：本发明涉及一种用于在多处理器系统中对总线的控制进行仲裁的方法。多处理器系统包括多个处理器和通过总线彼此耦合的主存储器，每个处理器包括由对应的处理器可访问并且与总线上的事务相关联的高速缓存存储器。该方法包括以下步骤：产生对总线的控制请求以及就一个请求授权总线的控制。公共汽车监控公交车上的预选交易活动; 并且在监视预选交易活动时，在总线上插入空闲周期。

9. 发明授权

US5553258A Method and apparatus for forming an exchange address for a system with different size caches 失效
标题翻译：用于形成具有不同大小的缓存的系统的交换地址的方法和装置
公开(公告)号：US5553258A
公开(公告)日：1996-09-03
申请号：US340125
申请日：1994-11-15
申请人： Nitin D. Godiwala , Kurt M. Thaller , Barry A. Maskas
发明人： Nitin D. Godiwala , Kurt M. Thaller , Barry A. Maskas
IPC分类号： G06F12/08
CPC分类号： G06F12/0833
摘要： The present invention is directed to a method and apparatus for performing exchange transactions between caches and a main memory of a computer system, the caches and main memory being coupled to one another by a bus. The method includes the steps of providing caches of different sizes with a cache having a smallest size, and with each cache having an index fixed as a function of the size of the cache. For each exchange transaction, the number of bits of an index used to address a selected cache location are determined, and the upper bits of a memory address from a tag store location corresponding to the selected cache location are retrieved, where the retrieved upper address bits form an exchange address. In the event that the index of the selected cache location comprises more bits than the index of the cache having the fewest addressable locations, the excess bits of the index of the selected cache location are appended to the exchange address. The cache then transmits the exchange address, a memory read address, and exchange data to memory.
摘要翻译：本发明涉及一种用于执行高速缓存和计算机系统的主存储器之间的交换事务的方法和装置，所述高速缓存和主存储器通过总线彼此耦合。该方法包括以下步骤：提供具有最小尺寸的高速缓存的不同大小的高速缓冲存储器，并且每个高速缓冲存储器具有根据高速缓存大小固定的索引。对于每个交换事务，确定用于寻址所选高速缓存位置的索引的位数，并且检索来自与所选高速缓存位置相对应的标签存储位置的存储器地址的高位，其中检索到的高位址位形成交换地址。在所选高速缓存位置的索引包括比具有最少可寻址位置的高速缓存索引更多位的情况下，所选高速缓存位置的索引的多余比特被附加到交换地址。高速缓存然后发送交换地址，存储器读地址和交换数据到存储器。

10. 发明授权

US5287517A Self-compensating voltage level shifting circuit 失效
标题翻译：自补偿电压电平移位电路
公开(公告)号：US5287517A
公开(公告)日：1994-02-15
申请号：US874322
申请日：1992-04-24
申请人： Barry A. Maskas , Jeffrey A. Metzger , George J. Harris
发明人： Barry A. Maskas , Jeffrey A. Metzger , George J. Harris
IPC分类号： H03K19/003 , H03K19/0185
CPC分类号： H03K19/018521 , H03K19/00384
摘要： The present invention is a circuit for converting the logic voltage levels from those of a first device to those of a second device. This conversion is accomplished while substantially isolating the second device from the effects of the first device that could influence the outputs of the second device that represent the converted logic level voltages.
摘要翻译：用于将逻辑电压电平从第一器件的电压电平转换为第二器件的逻辑电压电平的电路。实现这一转换，同时基本上将第二装置与第一装置的影响相分离，这可能影响表示转换的逻辑电平电压的第二装置的输出。

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