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1. 发明申请

US20130162290A1 PARTIAL RECONFIGURATION CIRCUITRY 有权
标题翻译：部分重构电路
公开(公告)号：US20130162290A1
公开(公告)日：2013-06-27
申请号：US13481506
申请日：2012-05-25
申请人： Balaji Margabandu , Dirk A. Reese , Leo Min Maung , Ninh D. Ngo
发明人： Balaji Margabandu , Dirk A. Reese , Leo Min Maung , Ninh D. Ngo
IPC分类号： H03K19/173
CPC分类号： H03K19/17756 , H03K19/1776
摘要： Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring a portion of a memory array. The PR circuitry may include a host circuit, a control circuit, an address register, and first, second, and third data registers. The host circuit may send a series of PR instructions to the control circuit. The control circuit may include a decompression circuit for decompressing compressed instructions, a decryption circuit for decrypting encrypted instructions, an error checking circuit for detecting errors in the instructions, and a logic circuit. The address register may select a desired frame. The selected frame may be loaded into the third data register. The contents of the third data register may be shifted into the first data register. The contents of the first data register may be modified according to a desired logic function using the logic circuit, shifted into the second data register, and written into the selected frame.
摘要翻译：集成电路可以包括用于重新配置存储器阵列的一部分的部分重配置（PR）电路。 PR电路可以包括主机电路，控制电路，地址寄存器以及第一，第二和第三数据寄存器。主机电路可以向控制电路发送一系列PR指令。控制电路可以包括用于解压缩压缩指令的解压缩电路，用于解密加密指令的解密电路，用于检测指令中的错误的错误检查电路和逻辑电路。地址寄存器可以选择所需的帧。所选择的帧可以被加载到第三数据寄存器中。第三数据寄存器的内容可以被移位到第一数据寄存器中。可以使用移入第二数据寄存器的逻辑电路根据期望的逻辑功能修改第一数据寄存器的内容，并写入所选择的帧。

2. 发明授权

US08797061B2 Partial reconfiguration circuitry 有权
标题翻译：部分重配置电路
公开(公告)号：US08797061B2
公开(公告)日：2014-08-05
申请号：US13481506
申请日：2012-05-25
申请人： Balaji Margabandu , Dirk A. Reese , Leo Min Maung , Ninh D. Ngo
发明人： Balaji Margabandu , Dirk A. Reese , Leo Min Maung , Ninh D. Ngo
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17756 , H03K19/1776
摘要： Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring a portion of a memory array. The PR circuitry may include a host circuit, a control circuit, an address register, and first, second, and third data registers. The host circuit may send a series of PR instructions to the control circuit. The control circuit may include a decompression circuit for decompressing compressed instructions, a decryption circuit for decrypting encrypted instructions, an error checking circuit for detecting errors in the instructions, and a logic circuit. The address register may select a desired frame. The selected frame may be loaded into the third data register. The contents of the third data register may be shifted into the first data register. The contents of the first data register may be modified according to a desired logic function using the logic circuit, shifted into the second data register, and written into the selected frame.
摘要翻译：集成电路可以包括用于重新配置存储器阵列的一部分的部分重配置（PR）电路。 PR电路可以包括主机电路，控制电路，地址寄存器以及第一，第二和第三数据寄存器。主机电路可以向控制电路发送一系列PR指令。控制电路可以包括用于解压缩压缩指令的解压缩电路，用于解密加密指令的解密电路，用于检测指令中的错误的错误检查电路和逻辑电路。地址寄存器可以选择所需的帧。所选择的帧可以被加载到第三数据寄存器中。第三数据寄存器的内容可以被移位到第一数据寄存器中。可以使用移入第二数据寄存器的逻辑电路根据期望的逻辑功能修改第一数据寄存器的内容，并写入所选择的帧。

3. 发明授权

US07924049B1 Accelerated programming technique for integrated circuits 有权
标题翻译：集成电路加速编程技术
公开(公告)号：US07924049B1
公开(公告)日：2011-04-12
申请号：US11960520
申请日：2007-12-19
申请人： Keith Duwel , Balaji Margabandu , Dirk A. Reese , Leo Min Maung
发明人： Keith Duwel , Balaji Margabandu , Dirk A. Reese , Leo Min Maung
IPC分类号： H03K19/173
CPC分类号： H03K19/17704 , H03K19/1774 , H03K19/17744 , H03K19/17776
摘要： Provided is a method and system to transmit data to a configurable integrated circuit that features delaying a capture edge of a clock signal at a data latch to synchronize the receipt of data at the data latch that was transmitted in response to a storage device receiving a launch edge of the clock signal. The method includes transmitting the clock signal having the launch edge and the capture edge to the storage device. The data is launched from the storage device to the integrated circuit in response to the storage device sensing the launch edge. Receipt of the capture edge at the data latch is delayed for a predetermined time to compensate for a delay between transmitting the launch edge and launching the data to ensure the data is latched by the data latch. Also disclosed is a system that carries out the function of the method.
摘要翻译：提供了一种将数据发送到可配置集成电路的方法和系统，其特征在于延迟数据锁存器处的时钟信号的捕获边沿，以同步在响应于接收发射的存储设备发送的数据锁存器处的数据的接收时钟信号的边沿。该方法包括将具有发射边缘和捕获边缘的时钟信号发送到存储设备。响应于感测发射边缘的存储设备，数据从存储设备发射到集成电路。在数据锁存器处的捕获边缘的接收被延迟预定时间以补偿发送发射边缘和发射数据之间的延迟，以确保数据被数据锁存器锁存。还公开了执行该方法的功能的系统。

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