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1. 发明申请

WO2010017512A2 ENHANCED RELIABILITY FOR SEMICONDUCTOR DEVICES USING DIELECTRIC ENCASEMENT 审中-公开
标题翻译：用电介质加载提高半导体器件的可靠性
公开(公告)号：WO2010017512A2
公开(公告)日：2010-02-11
申请号：PCT/US2009053205
申请日：2009-08-07
申请人： FLIPCHIP INT LLC , RECHE JOHN J H , JOHNSON MICHAEL E , BURGESS GUY F , CURTIS ANTHONY P , LICHTENTHAL STUART
发明人： RECHE JOHN J H , JOHNSON MICHAEL E , BURGESS GUY F , CURTIS ANTHONY P , LICHTENTHAL STUART
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H01L24/11 , H01L23/293 , H01L23/564 , H01L24/05 , H01L24/13 , H01L24/94 , H01L2224/0401 , H01L2224/05567 , H01L2224/0558 , H01L2224/05644 , H01L2224/1131 , H01L2224/11334 , H01L2224/1148 , H01L2224/13007 , H01L2224/13022 , H01L2224/131 , H01L2224/16 , H01L2224/274 , H01L2924/00013 , H01L2924/0002 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2224/13099 , H01L2224/05552
摘要： A method and device for enhanced reliability for semiconductor devices using dielectric encasement is disclosed. The method and device are directed to improving the reliability of the solder joint that connects the integrated circuit (IC) chip to the substrate. The method comprises applying a layer of a photoimageable permanent dielectric material to a top surface of the semiconductor device, and patterning the layer of the photoimageable permanent dielectric material to have an opening over each feature. The method further comprises dispensing or stencil printing fluxing material into the permanent dielectric material openings, and applying solder, which contains no flux, to a top surface of the fluxing material. In one or more embodiments, the method further comprises heating the semiconductor device to a reflow temperature appropriate for the reflow of the solder, thereby causing the solder to conform to sidewalls of the permanent dielectric material openings to form a protective seal.
摘要翻译：公开了一种用于使用电介质外壳增强半导体器件的可靠性的方法和设备。该方法和装置旨在改善将集成电路（IC）芯片连接到衬底的焊接点的可靠性。该方法包括将可光成像永久介电材料层施加到半导体器件的顶表面，并且将可光成像永久介电材料层图案化以在每个结构上具有开口。该方法还包括将助焊材料分配或模版印刷到永久介电材料开口中，并且将不含助焊剂的焊料施加到助熔材料的顶表面。在一个或多个实施例中，该方法还包括将半导体器件加热到适合于焊料回流的回流温度，由此使得焊料符合永久电介质材料开口的侧壁以形成保护性密封。

2. 发明申请

WO2011002778A2 METHODS AND STRUCTURES FOR A VERTICAL PILLAR INTERCONNECT 审中-公开
标题翻译：垂直柱连接的方法和结构
公开(公告)号：WO2011002778A2
公开(公告)日：2011-01-06
申请号：PCT/US2010040410
申请日：2010-06-29
申请人： FLIPCHIP INT LLC , BURGESS GUY F , CURTIS ANTHONY , JOHNSON MICHAEL E , STOUT GENE , TESSIER THEODORE G
发明人： BURGESS GUY F , CURTIS ANTHONY , JOHNSON MICHAEL E , STOUT GENE , TESSIER THEODORE G
IPC分类号： H01L21/60 , H01L23/488
CPC分类号： H01L24/11 , H01L21/563 , H01L24/03 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L2224/0345 , H01L2224/03464 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/1132 , H01L2224/11462 , H01L2224/1147 , H01L2224/11472 , H01L2224/11474 , H01L2224/11505 , H01L2224/1184 , H01L2224/11849 , H01L2224/119 , H01L2224/11901 , H01L2224/11903 , H01L2224/13012 , H01L2224/13013 , H01L2224/13014 , H01L2224/13024 , H01L2224/13082 , H01L2224/13083 , H01L2224/13101 , H01L2224/13111 , H01L2224/13116 , H01L2224/13117 , H01L2224/13118 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13294 , H01L2224/133 , H01L2224/13339 , H01L2224/1403 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/81191 , H01L2224/81815 , H01L2224/8184 , H01L2224/831 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01051 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/381 , H01L2924/01028 , H01L2924/0105 , H01L2924/01048 , H01L2924/01032 , H01L2924/00014 , H01L2924/00012
摘要： In wafer-level chip-scale packaging and flip-chip packaging and assemblies, a solder cap is formed on a vertical pillar. In one embodiment, the vertical pillar overlies a semiconductor substrate. A solder paste, which may be doped with at least one trace element, is applied on a top surface of the pillar structure. A reflow process is performed after applying the solder paste to provide the solder cap.
摘要翻译：在晶片级芯片级封装和倒装芯片封装和组装中，在垂直柱上形成焊锡帽。在一个实施例中，垂直柱覆盖半导体衬底。可以在柱结构的顶表面上施加可以掺杂有至少一个微量元素的焊膏。在施加焊膏以提供焊锡帽之后进行回流工艺。

3. 发明申请

WO2010017512A3 ENHANCED RELIABILITY FOR SEMICONDUCTOR DEVICES USING DIELECTRIC ENCASEMENT 审中-公开
公开(公告)号：WO2010017512A3
公开(公告)日：2010-02-11
申请号：PCT/US2009/053205
申请日：2009-08-07
申请人： FLIPCHIP INTERNATIONAL, LLC , RECHE, John, J., H. , JOHNSON, Michael, E. , BURGESS, Guy, F. , CURTIS, Anthony, P. , LICHTENTHAL, Stuart
发明人： RECHE, John, J., H. , JOHNSON, Michael, E. , BURGESS, Guy, F. , CURTIS, Anthony, P. , LICHTENTHAL, Stuart
IPC分类号： H01L21/60 , H01L23/48
摘要： A method and device for enhanced reliability for semiconductor devices using dielectric encasement is disclosed. The method and device are directed to improving the reliability of the solder joint that connects the integrated circuit (IC) chip to the substrate. The method comprises applying a layer of a photoimageable permanent dielectric material to a top surface of the semiconductor device, and patterning the layer of the photoimageable permanent dielectric material to have an opening over each feature. The method further comprises dispensing or stencil printing fluxing material into the permanent dielectric material openings, and applying solder, which contains no flux, to a top surface of the fluxing material. In one or more embodiments, the method further comprises heating the semiconductor device to a reflow temperature appropriate for the reflow of the solder, thereby causing the solder to conform to sidewalls of the permanent dielectric material openings to form a protective seal.

4. 发明申请

WO2008118193A3 WAFER-LEVEL INTERCONNECT FOR HIGH MECHANICAL RELIABILITY APPLICATIONS 审中-公开
标题翻译： WAFER-LEVEL INTERCONNECT高机械可靠性应用
公开(公告)号：WO2008118193A3
公开(公告)日：2008-10-02
申请号：PCT/US2007/080558
申请日：2007-10-05
申请人： FLIPCHIP INTERNATIONAL, LLC , CURTIS, Anthony , BURGESS, Guy, F. , JOHNSON, Michael , TESSIER, Ted , YU, Yuan
发明人： CURTIS, Anthony , BURGESS, Guy, F. , JOHNSON, Michael , TESSIER, Ted , YU, Yuan
IPC分类号： H01L21/4763
摘要： The structure described herein incorporates an interconnect positioned between two spaced electrical contacts. The interconnect comprises a lead (Pb)-free solder alloy consisting essentially of nickel (Ni), tin (Sn), silver (Ag), and copper (Cu). The nickel (Ni) content is sufficient to produce a smooth interfacial IMC layer in an under bump metallurgy (UBM) when disposed between the two contacts. An embodiment of the structure described herein is a device comprising a substrate, an under bump metallurgy (UBM) disposed on the substrate, a bulk solder body disposed on the under bump metallurgy (UBM), and a wafer device connected to the under bump metallurgy (UBM) through the bulk solder body. The bulk solder body comprises of nickel (Ni), tin (Sn), silver (Ag), and copper (Cu). The nickel (Ni) is in a range of 0.01 to 0.20 percent by weight (wt%).
摘要翻译：这里描述的结构结合了位于两个隔开的电触点之间的互连。该互连包括基本上由镍（Ni），锡（Sn），银（Ag）和铜（Cu）组成的无铅（Pb）焊料合金。当置于两个触点之间时，镍（Ni）含量足以在凸块下冶金（UBM）中产生光滑的界面IMC层。本文描述的结构的实施例是包括衬底，设置在衬底上的凸块下金属冶金（UBM），设置在凸块下金属冶金（UBM）上的块体焊料主体以及连接到凸块下金属冶金（UBM）通过散装焊锡体。本体焊料主体由镍（Ni），锡（Sn），银（Ag）和铜（Cu）组成。镍（Ni）的重量百分比为0.01-0.20％（重量百分比）。

5. 发明申请

WO2011002778A3 METHODS AND STRUCTURES FOR A VERTICAL PILLAR INTERCONNECT 审中-公开
公开(公告)号：WO2011002778A3
公开(公告)日：2011-01-06
申请号：PCT/US2010/040410
申请日：2010-06-29
申请人： FLIPCHIP INTERNATIONAL, LLC , BURGESS, Guy F. , CURTIS, Anthony , JOHNSON, Michael E , STOUT, Gene , TESSIER, Theodore G.
发明人： BURGESS, Guy F. , CURTIS, Anthony , JOHNSON, Michael E , STOUT, Gene , TESSIER, Theodore G.
IPC分类号： H01L21/60 , H01L23/488
摘要： In wafer-level chip-scale packaging and flip-chip packaging and assemblies, a solder cap is formed on a vertical pillar. In one embodiment, the vertical pillar overlies a semiconductor substrate. A solder paste, which may be doped with at least one trace element, is applied on a top surface of the pillar structure. A reflow process is performed after applying the solder paste to provide the solder cap.

6. 发明申请

WO2008118193A2 WAFER-LEVEL INTERCONNECT FOR HIGH MECHANICAL RELIABILITY APPLICATIONS 审中-公开
标题翻译：高机械可靠性应用的水平互联
公开(公告)号：WO2008118193A2
公开(公告)日：2008-10-02
申请号：PCT/US2007080558
申请日：2007-10-05
申请人： FLIPCHIP INT LLC , CURTIS ANTHONY , BURGESS GUY F , JOHNSON MICHAEL , TESSIER TED , YU YUAN
发明人： CURTIS ANTHONY , BURGESS GUY F , JOHNSON MICHAEL , TESSIER TED , YU YUAN
IPC分类号： H01L23/538
CPC分类号： H01L24/10 , B23K35/262 , B23K2201/36 , C22C13/00 , H01L24/13 , H01L2224/0401 , H01L2224/05124 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05171 , H01L2224/0558 , H01L2224/05644 , H01L2224/05647 , H01L2224/13 , H01L2224/131 , H01L2224/16 , H01L2924/00013 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H05K3/3463 , H01L2224/13099 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： The structure described herein incorporates an interconnect positioned between two spaced electrical contacts. The interconnect comprises a lead (Pb)-free solder alloy consisting essentially of nickel (Ni), tin (Sn), silver (Ag), and copper (Cu). The nickel (Ni) content is sufficient to produce a smooth interfacial IMC layer in an under bump metallurgy (UBM) when disposed between the two contacts. An embodiment of the structure described herein is a device comprising a substrate, an under bump metallurgy (UBM) disposed on the substrate, a bulk solder body disposed on the under bump metallurgy (UBM), and a wafer device connected to the under bump metallurgy (UBM) through the bulk solder body. The bulk solder body comprises of nickel (Ni), tin (Sn), silver (Ag), and copper (Cu). The nickel (Ni) is in a range of 0.01 to 0.20 percent by weight (wt%).
摘要翻译：本文描述的结构包括位于两个间隔开的电触点之间的互连。互连包括基本上由镍（Ni），锡（Sn），银（Ag）和铜（Cu）组成的无铅（Pb）焊料合金。当设置在两个触点之间时，镍（Ni）含量足以在凸块下冶金（UBM）中产生平滑的界面IMC层。本文所述的结构的一个实施例是一种器件，包括衬底，设置在衬底上的凸块下金属（UBM），设置在凸块下金属（UBM）上的体焊料体）和连接到凸块下的冶金（UBM）通过大块焊料体。大块焊料体由镍（Ni），锡（Sn），银（Ag）和铜（Cu）构成。镍（Ni）的含量在0.01〜0.20重量％的范围内。

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