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1. 发明申请

WO2011008215A1 VIRTUAL HOT INSERTING FUNCTIONS IN A SHARED I/O ENVIRONMENT 审中-公开
标题翻译：共享I / O环境中的虚拟热插入功能
公开(公告)号：WO2011008215A1
公开(公告)日：2011-01-20
申请号：PCT/US2009/050995
申请日：2009-07-17
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , MATTHEWS, David, L. , BRINKMANN, Hubert, E. , BROWNELL, Paul, V. , BASILE, Barry, S.
发明人： MATTHEWS, David, L. , BRINKMANN, Hubert, E. , BROWNELL, Paul, V. , BASILE, Barry, S.
IPC分类号： G06F15/16 , G06F13/14
CPC分类号： G06F13/4081 , G06F2213/0026 , H04L12/4625
摘要： A blade server system and method for virtually hot plugging and virtually hot removing functions in a shared I/O environment. A management node physically hot inserts and hot removes an I/O node in the server system without a compute node being aware of the hot insert and hot removal. The management node and the compute node create and remove virtual links between the compute node and the virtual functions.
摘要翻译：用于在共享I / O环境中实际热插拔和实际热删除功能的刀片服务器系统和方法。管理节点物理上热插拔和热删除服务器系统中的I / O节点，而计算节点不知道热插拔和热删除。管理节点和计算节点在计算节点和虚拟功能之间创建和删除虚拟链路。

2. 发明申请

WO2009120187A2 SYSTEM AND METHOD FOR TRANSFORMING PCIE SR-IOV FUNCTIONS TO APPEAR AS LEGACY FUNCTIONS 审中-公开
标题翻译：用于改变PCIE SR-IOV功能的系统和方法作为LEGACY功能
公开(公告)号：WO2009120187A2
公开(公告)日：2009-10-01
申请号：PCT/US2008058110
申请日：2008-03-25
申请人： HEWLETT PACKARD DEVELOPMENT CO , BRINKMANN HUBERT E , CAGLE JOHN M , BASILE BARRY S , MATTHEWS DAVID L , BROWNELL PAUL V , DOSS WILLIAM F
发明人： BRINKMANN HUBERT E , CAGLE JOHN M , BASILE BARRY S , MATTHEWS DAVID L , BROWNELL PAUL V , DOSS WILLIAM F
CPC分类号： G06F13/404 , G06F2213/0024 , G06F2213/0026 , G06F2213/0058
摘要： The invention is related to a novel primate specific brain isoform of the potassium channel KCNH2 and genetic association with risk for schizophrenia. A system for transforming a single root input/output virtualization (SR-IOV) function to appear as a legacy function, and a corresponding method includes a switch platform coupled between a legacy host and a SR-IOV-enabled device. The switch platform includes a processor programmed to discern configuration cycles by type and to process the configuration cycles, and one or more local registers that store data related to the configuration cycles. The system further includes a control module coupled to the switch platform, the control module supervising operation of the switch platform.
摘要翻译：本发明涉及钾通道KCNH2的新型灵长类动物特异性脑同种型和与精神分裂症风险的遗传相关性。用于转换单个根输入/输出虚拟化（SR-IOV）功能以呈现为传统功能的系统，以及相应的方法包括耦合在传统主机和启用SR-IOV的设备之间的交换平台。交换机平台包括处理器，其被编程为通过类型识别配置周期并处理配置周期，以及存储与配置周期相关的数据的一个或多个本地寄存器。该系统还包括耦合到开关平台的控制模块，控制模块监控开关平台的操作。

3. 发明申请

WO2009108146A1 METHOD AND APPARATUS FOR PERFORMING A HOST ENUMERATION PROCESS 审中-公开
标题翻译：用于执行主体计算过程的方法和装置
公开(公告)号：WO2009108146A1
公开(公告)日：2009-09-03
申请号：PCT/US2008/002526
申请日：2008-02-26
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY L.P. , MATTHEWS, David, L. , BRINKMANN, Hubert, E. , BASILE, Barry, S. , BROWNELL, Paul, V. , DEPEW, Kevin, G.
发明人： MATTHEWS, David, L. , BRINKMANN, Hubert, E. , BASILE, Barry, S. , BROWNELL, Paul, V. , DEPEW, Kevin, G.
IPC分类号： G06F13/14
CPC分类号： G06F13/385 , G06F9/4401 , G06F9/4411 , G06F13/4022 , G06F13/4027 , G06F2213/0052 , H04L29/08144 , H04L41/0213
摘要： A method and apparatus for host enumeration process. One embodiment of the method provides a bit to indicate to the host whether enumeration process should start or continue. The bit may be set when the shared resource process has been successfully completed, or the bit may be set if too much time has elapsed since the shared resource process has started, or the bit may be set if too much time has elapsed before the shared resource process is started, or the bit may be set if the shared resource process has not been performed successfully, or the bit may be set if the port is open and it is unnecessary to perform the shared resource process.
摘要翻译：一种用于主机枚举过程的方法和装置。该方法的一个实施例提供一点以向主机指示枚举过程是应该开始还是继续。当共享资源处理已经成功完成时，可以设置该位，或者如果从共享资源处理开始以来已经过了太多时间，则可以设置该位，或者如果在共享资源处理之前经过了太多时间资源处理开始，或者如果共享资源处理未成功执行，则可以设置该位，或者如果端口是打开的，并且不必执行共享资源处理，则可以设置该位。

4. 发明申请

WO2009151447A1 PRESENTING MULTI-FUNCTION DEVICES BEHIND A SWITCH HIERARCHY AS A SINGLE FUNCTION DEVICE 审中-公开
标题翻译：将多功能设备呈现为单功能设备的开关层级
公开(公告)号：WO2009151447A1
公开(公告)日：2009-12-17
申请号：PCT/US2008/066442
申请日：2008-06-10
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , MATTHEWS, David L. , BRINKMANN, Hubert E. , DIHN, James Xuan , RILEY, Dwight D. , BROWNELL, Paul V.
发明人： MATTHEWS, David L. , BRINKMANN, Hubert E. , DIHN, James Xuan , RILEY, Dwight D. , BROWNELL, Paul V.
IPC分类号： H04L12/28
CPC分类号： H04L12/28 , G06F13/4027
摘要： In one embodiment, a computer system, comprises at least one host node, at least one input/output node coupled to the host node, at least one multi-function device coupled to the input/output node via a switch, and a middle manager processor comprising logic to block an enumeration process in a host node for the multi-function devices behind the switch hierarchy, initiate an enumeration process for the multi-function devices in a manager processor separate from the host node, store a routing table for the switch hierarchy in a memory module coupled to the manager processor, and allocate, in the manager processor, endpoint device resources to the host node.
摘要翻译：在一个实施例中，计算机系统包括至少一个主机节点，耦合到主机节点的至少一个输入/输出节点，经由交换机耦合到输入/输出节点的至少一个多功能设备，以及中间管理器处理器包括用于阻止主机节点中用于交换机层级后面的多功能设备的枚举过程的逻辑，为与主机节点分离的管理器处理器中的多功能设备启动枚举过程，存储用于交换机的路由表耦合到管理器处理器的存储器模块中的层次结构，并且在管理器处理器中将端点设备资源分配给主机节点。

5. 发明申请

WO2009134218A1 VIRTUAL-INTERRUPT-MODE INTERFACE AND METHOD FOR VIRTUALIZING AN INTERRUPT MODE 审中-公开
标题翻译：用于虚拟化中断模式的虚拟中断模式接口和方法
公开(公告)号：WO2009134218A1
公开(公告)日：2009-11-05
申请号：PCT/US2008/005448
申请日：2008-04-28
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , BRINKMANN, Hubert E. , BROWNELL, Paul V. , MATTHEWS, David L. , RILEY, Dwight D.
发明人： BRINKMANN, Hubert E. , BROWNELL, Paul V. , MATTHEWS, David L. , RILEY, Dwight D.
IPC分类号： G06F13/24 , G06F13/38 , G06F13/42
CPC分类号： G06F13/24 , G06F9/45558 , G06F2009/45579 , G06F2213/0026
摘要： Embodiments of the present invention are directed to methods for virtualizing interrupt modes on behalf of interrupt-generating devices, including I/O-device controllers, so that newer interrupt-generating devices that lack older interrupt modes can be used in systems that continue to rely on older interrupt modes. In one embodiment of the present invention, a PCIe switch or PCIe-based host bridge is modified, or a new component introduced, to provide an interrupt-mode virtualizing function, or virtual interrupt-mode interface, that provides a virtual interrupt mode on behalf of interrupt-generating devices, such as I/O-device controllers, to operating systems, BIOS layers, and other components that communicate with the I/O-device controllers.
摘要翻译：本发明的实施例涉及用于代表包括I / O设备控制器的中断产生设备虚拟化中断模式的方法，使得缺少较旧的中断模式的较新的中断产生设备可以在继续依赖的系统中使用在较老的中断模式下。在本发明的一个实施例中，改进了PCIe交换机或基于PCIe的主桥，或者引入了新的组件来提供代表虚拟中断模式的中断模式虚拟化功能或虚拟中断模式接口诸如I / O设备控制器的中断产生设备到操作系统，BIOS层以及与I / O设备控制器通信的其他组件。

6. 发明申请

WO2009105095A1 REDRIVER WITH TWO REFERENCE CLOCKS AND METHOD OF OPERATION THEREOF 审中-公开
标题翻译：具有两个参考时钟的REDRIVER及其操作方法
公开(公告)号：WO2009105095A1
公开(公告)日：2009-08-27
申请号：PCT/US2008/054399
申请日：2008-02-20
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , LAI, Ho, M. , SIDES, Chi, K. , BROWNELL, Paul, V.
发明人： LAI, Ho, M. , SIDES, Chi, K. , BROWNELL, Paul, V.
IPC分类号： G06F1/06
CPC分类号： G06F5/06
摘要： A two reference clock architected redriver includes an inbound elastic buffer and an outbound elastic buffer. Data transmitted to and received from a North Bridge uses a common reference clock architecture. Data transmitted to and received from an external blade uses a separate reference clock architecture. The inbound elastic buffer includes an inbound elastic buffer recovered clock domain, an inbound elastic buffer common reference clock domain, and an inbound decoder/descrambler, an inbound scrambler/encoder, and inbound liner shift registers. The outbound elastic buffer includes an outbound elastic buffer common reference clock domain, an outbound elastic buffer low jitter clock domain, and an outbound decoder/descrambler, an outbound scrambler/encoder, and outbound liner shift register.
摘要翻译：两个参考时钟架构的重拨器包括入站弹性缓冲器和出站弹性缓冲器。发送到北桥和从北桥接收的数据使用公共参考时钟架构。从外部刀片传输和接收的数据使用单独的参考时钟架构。入站弹性缓冲器包括入站弹性缓冲器恢复时钟域，入站弹性缓冲器公共参考时钟域和入站解码器/解扰器，入站加扰器/编码器和入站班轮移位寄存器。出站弹性缓冲器包括出站弹性缓冲器公共参考时钟域，出站弹性缓冲器低抖动时钟域和出站解码器/解扰器，出站扰码器/编码器和出站线性移位寄存器。

7. 发明申请

WO2009120187A3 SYSTEM AND METHOD FOR TRANSFORMING PCIE SR-IOV FUNCTIONS TO APPEAR AS LEGACY FUNCTIONS 审中-公开
公开(公告)号：WO2009120187A3
公开(公告)日：2009-10-01
申请号：PCT/US2008/058110
申请日：2008-03-25
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , BRINKMANN, Hubert E. , CAGLE, John M. , BASILE, Barry S. , MATTHEWS, David L. , BROWNELL, Paul V. , DOSS, William F.
发明人： BRINKMANN, Hubert E. , CAGLE, John M. , BASILE, Barry S. , MATTHEWS, David L. , BROWNELL, Paul V. , DOSS, William F.
IPC分类号： G06F13/14
摘要： The invention is related to a novel primate specific brain isoform of the potassium channel KCNH 2 and genetic association with risk for schizophrenia. A system for transforming a single root input/output virtualization (SR-IOV) function to appear as a legacy function, and a corresponding method includes a switch platform coupled between a legacy host and a SR-IOV-enabled device. The switch platform includes a processor programmed to discern configuration cycles by type and to process the configuration cycles, and one or more local registers that store data related to the configuration cycles. The system further includes a control module coupled to the switch platform, the control module supervising operation of the switch platform.

8. 发明申请

WO2009017570A1 TRANSACTION FLOW CONTROL IN PCI EXPRESS FABRIC 审中-公开
标题翻译： PCI EXPRESS FABRIC的交易流量控制
公开(公告)号：WO2009017570A1
公开(公告)日：2009-02-05
申请号：PCT/US2008/008275
申请日：2008-07-03
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , BROWNELL, Paul V. , MATTHEWS, David L.
发明人： BROWNELL, Paul V. , MATTHEWS, David L.
IPC分类号： G06F13/00 , G06F15/16
CPC分类号： G06F13/4221
摘要： A computer-executed method (200) for controlling transaction flow in a network comprises communicating (202) transaction packets among a plurality of devices in a network fabric and subdividing (204) a memory into a plurality of memory segments for storing received transaction cycles according to transaction packet type comprising posted, non-posted, and completion cycles. A plurality of transaction cycles are received (206) in the memory segment plurality at a target device and transaction cycle priority is allocated (208) according to transaction packet type wherein posted cycles have highest priority. Cycles are retrieved (210) from the memory segment plurality in an order determined by priority.
摘要翻译：用于控制网络中的事务流的计算机执行方法（200）包括在网络结构中的多个设备之间通信（202）事务分组，并将存储器细分（204）为多个存储器段，用于存储接收的事务循环，包括发布，未发布和完成周期的事务数据包类型。在目标设备处的多个存储器段中接收多个事务周期（206），并且根据事务分组类型分配事务周期优先级（208），其中发布周期具有最高优先级。从优先级确定的顺序从多个存储器片段检索（210）循环。

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