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1. 发明申请

WO2011028981A1 A PROCESSING UNIT WITH A PLURALITY OF SHADER ENGINES 审中-公开
标题翻译：具有多个阴影发动机的加工单元
公开(公告)号：WO2011028981A1
公开(公告)日：2011-03-10
申请号：PCT/US2010/047779
申请日：2010-09-03
申请人： ADVANCED MICRO DEVICES, INC. , MANTOR, Michael , TAYLOR, Ralph, C. , BRADY, Jeffrey, T.
发明人： MANTOR, Michael , TAYLOR, Ralph, C. , BRADY, Jeffrey, T.
IPC分类号： G06T15/00
CPC分类号： G06T15/005
摘要： A processor includes a first shader engine and a second shader engine. The first shader engine is configured to process pixel shaders for a first subset of pixels to be displayed on a display device. The second shader engine is configured to process pixel shaders for a second subset of pixels to be displayed on the display device. Both the first and second shader engines are also configured to process general-compute shaders and non-pixel graphics shaders. The processor may also include a level-one (Ll) data cache, coupled to and positioned between the first and second shader
摘要翻译：处理器包括第一着色引擎和第二着色引擎。第一个着色引擎被配置为处理要在显示设备上显示的第一子像素的像素着色器。第二着色引擎被配置为处理要显示在显示设备上的第二子像素的像素着色器。第一个和第二个着色引擎都配置为处理通用计算着色器和非像素图形着色器。处理器还可以包括耦合到并定位在第一和第二着色器之间的一级（L1）数据高速缓存

2. 发明申请

WO2009145916A1 REDUNDANCY METHODS AND APPARATUS FOR SHADER COLUMN REPAIR 审中-公开
标题翻译：冗余方法和设备用于阴影柱修复
公开(公告)号：WO2009145916A1
公开(公告)日：2009-12-03
申请号：PCT/US2009/003314
申请日：2009-06-01
申请人： ADVANCED MICRO DEVICES, INC. , MANTOR, Michael, J. , BRADY, Jeffrey, T. , SOCARRAS, Angel, E.
发明人： MANTOR, Michael, J. , BRADY, Jeffrey, T. , SOCARRAS, Angel, E.
IPC分类号： G09G5/00
CPC分类号： G06T15/005 , G06F11/2038 , G06F11/2043
摘要： A method and apparatus for shader data repair utilizing a Redundant Shader Switch (RSS). The RSS consists of an input and output section whereby when a defective shader pipe is detected, the RSS multiplexes shader pipe data destined to the defective shader pipe to a redundant shader pipe array for processing. Once processed, the shader pipe data is multiplexed back to the RSS where the processed shader pipe data is directed to the corresponding output column of the RSS. The RSS contains delay pipes used to re-align and synchronize the repaired shader pipe data with output export data.
摘要翻译：使用冗余着色器开关（RSS）的着色器数据修复的方法和装置。 RSS由输入和输出部分组成，当检测到有缺陷的着色管时，RSS将去往有缺陷的着色管的着色管数据复用到冗余着色管阵列进行处理。一旦处理，着色器管道数据被复用回RSS，其中处理的着色器管道数据被引导到RSS的相应输出列。 RSS包含用于重新对齐并同步修复的着色器管道数据和输出导出数据的延迟管道。

3. 发明申请

WO2009145918A1 SCALABLE AND UNIFIED COMPUTE SYSTEM 审中-公开
标题翻译：可扩展和统一的计算机系统
公开(公告)号：WO2009145918A1
公开(公告)日：2009-12-03
申请号：PCT/US2009/003316
申请日：2009-06-01
申请人： ADVANCED MICRO DEVICES, INC. , MANTOR, Michael, J. , BRADY, Jeffrey, T. , FOWLER, Mark, C. , ZINI, Marcos, P.
发明人： MANTOR, Michael, J. , BRADY, Jeffrey, T. , FOWLER, Mark, C. , ZINI, Marcos, P.
IPC分类号： G09G5/00
CPC分类号： G06T15/005 , G06T15/04 , G09G5/363 , G09G2360/121 , G09G2360/125
摘要： A Scalable and Unified Compute System performs scalable, repairable general purpose and graphics shading operations, memory load/store operations and texture filtering. A Scalable and Unified Compute Unit Module comprises a shader pipe array, a texture mapping unit, and a level one texture cache system. The Scalable and Unified Compute Unit Module accepts ALU instructions, input/output instructions, and texture or memory requests for a specified set of pixels, vertices, primitives, surfaces, or general compute work items from a shader program and performs associated operations to compute the programmed output data. The texture mapping unit accepts source data addresses and instruction constants in order to fetch, format, and perform instructed filtering interpolations to generate formatted results based on the specific corresponding data stored in a level one texture cache system. The texture mapping unit consists of an address generating system, a pre-formatter module, interpolator module, accumulator module and a format module. A method for a Scalable and Unified Compute System is also presented.
摘要翻译：可扩展和统一的计算系统执行可扩展，可修复的通用和图形着色操作，存储器加载/存储操作和纹理过滤。可扩展和统一的计算单元模块包括着色器管阵列，纹理映射单元和一级纹理缓存系统。可扩展和统一的计算单元模块从着色器程序中接收ALU指令，输入/输出指令，以及指定的像素集，顶点，基元，曲面或一般计算工作项的纹理或存储器请求，并执行相关操作以计算编程输出数据。纹理映射单元接受源数据地址和指令常数，以便获取，格式化和执行指示的过滤内插，以基于存储在一级纹理缓存系统中的特定对应数据生成格式化的结果。纹理映射单元由地址生成系统，预格式化模块，插值器模块，累加器模块和格式模块组成。还提出了可扩展和统一计算系统的方法。

4. 发明申请

WO2012031177A1 METHOD AND APPARATUS FOR PERFORMING FLOATING-POINT DIVISION 审中-公开
标题翻译：用于执行浮点分割的方法和装置
公开(公告)号：WO2012031177A1
公开(公告)日：2012-03-08
申请号：PCT/US2011/050290
申请日：2011-09-02
申请人： ADVANCED MICRO DEVICES, INC. , CONYNGHAM, James , BRADY, Jeffrey, T. , SPENCER, Christopher, L.
发明人： CONYNGHAM, James , BRADY, Jeffrey, T. , SPENCER, Christopher, L.
IPC分类号： G06F9/30
CPC分类号： G06F7/4873 , G06F9/30014
摘要： A method and apparatus provides for performing floating-point division using input check/output correction floating-point division logic and a floating-point division fix-up instruction (e.g., an instruction, command, signal or other indicator). In one example, the apparatus includes a processor having a floating-point arithmetic logic unit (ALU) that includes the input check/output correction floating-point division logic. The input check/output correction floating-point division logic is responsive to the floating-point division fix-up instruction executable by the floating-point ALU that causes the input check/output correction floating-point division logic to examine a first input representing a numerator and a second input representing a denominator to determine whether a special case of floating-point division occurs. The floating-point division fix-up instruction also causes the input check/output correction floating-point division logic to provide an output representing a floating-point division result based on the determined special case of floating-point division and a third input representing a candidate quotient.
摘要翻译：一种方法和装置提供使用输入校验/输出校正浮点分割逻辑和浮点分割修正指令（例如，指令，命令，信号或其它指示符）执行浮点分割。在一个示例中，该装置包括具有包括输入校验/输出校正浮点分割逻辑的浮点运算逻辑单元（ALU）的处理器。输入检查/输出校正浮点除法逻辑响应于可由浮点ALU执行的浮点除法固定指令，该浮点ALU使得输入校验/输出校正浮点除法逻辑检查表示一个分子和表示分母的第二输入，以确定是否发生浮点分割的特殊情况。浮点分割固定指令还使得输入校验/输出校正浮点除法逻辑基于所确定的浮点除法的特殊情况来提供表示浮点分割结果的输出，第三输入表示候选商。

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