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    • 3. 发明授权
    • Latch-type sense amplifier
    • 锁存型读出放大器
    • US07227798B2
    • 2007-06-05
    • US10679941
    • 2003-10-06
    • Anuj GuptaSanjeev Chopra
    • Anuj GuptaSanjeev Chopra
    • G11C7/00
    • G11C7/065
    • An improved latch-type sense amplifier circuit having two cross-coupled inverters forming a latch, a supply coupling device for selectively connecting the latch to a supply source, and a bit line coupling circuits for selectively connecting the inputs of each inverter to the complimentary bit line from the memory array. The circuit is configured to sense a voltage difference between the bit lines with improved reliability by providing a delayed sense amplifier enable signal to pass transistors for delaying disconnection of the bit lines from the sense amplifier until the latching action is completed, and adding two transistors in series with the existing transistors of the conventional latch for correcting the offset between the threshold voltages of the inverters of the latch.
    • 具有形成锁存器的两个交叉耦合的反相器的改进的锁存型读出放大器电路,用于选择性地将锁存器连接到电源的电源耦合装置和用于选择性地将每个反相器的输入连接到补充位的位线耦合电路 线从内存阵列。 该电路被配置为通过提供延迟读出放大器使能信号来传递晶体管来延迟位线从读出放大器的断开直到闭锁动作完成,并且将两个晶体管加到 与常规锁存器的现有晶体管串联,用于校正锁存器的反相器的阈值电压之间的偏移。
    • 7. 发明申请
    • SYSTEM FOR BOUNDARY SCAN REGISTER CHAIN COMPRESSION
    • 边界扫描注册链压缩系统
    • US20110179325A1
    • 2011-07-21
    • US12687893
    • 2010-01-15
    • Anuj GuptaHimanshu Kukreja
    • Anuj GuptaHimanshu Kukreja
    • G01R31/3177G06F11/25
    • G01R31/318547
    • A system for testing input/output pads of an integrated circuit includes boundary scan register chains, a test control unit and a test data processing unit. Input test data is provided to the test control unit, which then provides the test data to the test data processing unit. The test data processing unit processes the test data to obtain processed test data. Thereafter, the processed data is loaded in each of the boundary scan register chains in parallel. The processed test data is propagated sequentially through the plurality of boundary scan register chains to obtain output test data. The output test data is used to detect faults present in the input/output pads of the integrated circuit.
    • 用于测试集成电路的输入/输出焊盘的系统包括边界扫描寄存器链,测试控制单元和测试数据处理单元。 输入测试数据提供给测试控制单元,测试控制单元然后将测试数据提供给测试数据处理单元。 测试数据处理单元处理测试数据以获得处理的测试数据。 此后,并行处理的数据被加载到每个边界扫描寄存器链中。 经处理的测试数据依次通过多个边界扫描寄存器链传播,以获得输出测试数据。 输出测试数据用于检测集成电路输入/输出焊盘中存在的故障。