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1. 发明授权

US09612194B2 Spectroscopic analysis of oil sands ore face for real time ore blend management 有权
公开(公告)号：US09612194B2
公开(公告)日：2017-04-04
申请号：US14131035
申请日：2012-07-09
申请人： Michael A. Davis , Andrew E. Carlson , David O. Winkowski , John V. Viega , Alan D. Kersey , Mark R. Fernald
发明人： Michael A. Davis , Andrew E. Carlson , David O. Winkowski , John V. Viega , Alan D. Kersey , Mark R. Fernald
IPC分类号： G01N21/27 , H04N5/33 , G01N21/31 , G01N33/24 , G01N21/3563 , G01G19/08 , G01N21/84 , G06T7/00
CPC分类号： G01N21/27 , G01G19/08 , G01N21/31 , G01N21/3563 , G01N21/84 , G01N33/241 , G01N2201/025 , G01N2201/08 , G01N2201/12 , G06T7/00 , G06T2207/30181 , H04N5/332
摘要： Apparatus is provided featuring a signal processor or signal processing module configured to receive signaling containing information about images of an ore sample; and determine information about a Bitumen Content of the ore sample based at least partly on the signaling, including for use in real time ore blend management in a bitumen recovery process related to mined oil sands. The ore sample may be an ore face, and the signaling may contain information about the images of the ore face. The signal processor or signal processing module may be configured to determine a real time ore face ore grade visualization based at least partly on the signaling, and provide corresponding signaling containing information about the real time ore face ore grade visualization, including a composite overlay image.

2. 发明申请

US20140347472A1 SPECTROSCOPIC ANALYSIS OF OIL SANDS ORE FACE FOR REAL TIME ORE BLEND MANAGEMENT 有权
标题翻译：用于实时ORE混合管理的油砂层的光谱分析
公开(公告)号：US20140347472A1
公开(公告)日：2014-11-27
申请号：US14131035
申请日：2012-07-09
申请人： Michael A. Davis , Andrew E. Carlson , David O. Winkowski , John V. Viega , Alan D. Kersey , Mark R. Fernald
发明人： Michael A. Davis , Andrew E. Carlson , David O. Winkowski , John V. Viega , Alan D. Kersey , Mark R. Fernald
IPC分类号： G01N21/27 , H04N5/33 , G01N21/31 , G06T7/00 , G01N21/84 , G01G19/08
CPC分类号： G01N21/27 , G01G19/08 , G01N21/31 , G01N21/3563 , G01N21/84 , G01N33/241 , G01N2201/025 , G01N2201/08 , G01N2201/12 , G06T7/00 , G06T2207/30181 , H04N5/332
摘要： Apparatus is provided featuring a signal processor or signal processing module configured to receive signaling containing information about images of an ore sample; and determine information about a Bitumen Content of the ore sample based at least partly on the signaling, including for use in real time ore blend management in a bitumen recovery process related to mined oil sands. The ore sample may be an ore face, and the signaling may contain information about the images of the ore face. The signal processor or signal processing module may be configured to determine a real time ore face ore grade visualization based at least partly on the signaling, and provide corresponding signaling containing information about the real time ore face ore grade visualization, including a composite overlay image.
摘要翻译：提供设备，其特征在于信号处理器或信号处理模块，其被配置为接收包含关于矿石样品的图像的信息的信令; 并且至少部分地基于信号确定矿石样品的沥青含量的信息，包括用于与开采的油砂相关的沥青回收过程中的实时矿石混合管理。矿石样品可以是矿石面，信号可以包含关于矿石图像的信息。信号处理器或信号处理模块可以被配置为至少部分地基于信令来确定实时矿石等级可视化，并且提供包含关于实时矿石等级可视化的信息的相应信令，包括复合覆盖图像。

3. 发明授权

US08258578B2 Handshake structure for improving layout density 有权
标题翻译：用于提高布局密度的握手结构
公开(公告)号：US08258578B2
公开(公告)日：2012-09-04
申请号：US12551019
申请日：2009-08-31
申请人： Andrew E. Carlson
发明人： Andrew E. Carlson
IPC分类号： H01L21/28
CPC分类号： H01L27/0207 , H01L21/76895 , H01L21/823456 , H01L21/823475 , H01L23/485 , H01L27/088 , H01L29/4238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a gate on a semiconductor substrate. One side wall of the gate may include at least one protrusion and an opposite side wall of the gate may include at least one depression. A contact is formed through an insulating layer disposed over the gate. The contact at least partially overlaps at least one of the protrusions in the gate. A metal layer is disposed on the insulating layer. The metal layer includes a first structure shifted to a first side of the gate. The first structure at least partially overlaps the contact such that the contact electrically couples the first structure to the gate through the insulating layer.
摘要翻译：半导体器件包括半导体衬底上的栅极。门的一个侧壁可以包括至少一个突起，并且门的相对的侧壁可以包括至少一个凹陷。通过设置在栅极上方的绝缘层形成接触。接触件至少部分地与栅极中的至少一个突起重叠。金属层设置在绝缘层上。金属层包括偏移到栅极的第一侧的第一结构。第一结构至少部分地重叠接触，使得接触件通过绝缘层将第一结构电耦合到栅极。

4. 发明申请

US20110198677A1 SYSTEMS AND METHODS FOR A CONTINUOUS-WELL DECOUPLING CAPACITOR 有权
标题翻译：一种连续良好的解压电容器的系统和方法
公开(公告)号：US20110198677A1
公开(公告)日：2011-08-18
申请号：US12705185
申请日：2010-02-12
申请人： Andrew E. Carlson
发明人： Andrew E. Carlson
IPC分类号： H01L27/06 , H01L21/02 , G06F17/00
CPC分类号： H01L29/94 , H01L27/0805 , H01L27/0811
摘要： A decoupling capacitor includes a pair of MOS capacitors formed in wells of opposite plurality. Each MOS capacitor has a set of well-ties and a high-dose implant, allowing high frequency performance under accumulation or depletion biasing. The top conductor of each MOS capacitor is electrically coupled to the well-ties of the other MOS capacitor and biased consistently with logic transistor wells. The well-ties and/or the high-dose implants of the MOS capacitors exhibit asymmetry with respect to their dopant polarities.
摘要翻译：去耦电容器包括形成在相反多个孔中的一对MOS电容器。每个MOS电容器具有一系列的适应性和高剂量的植入物，可以在积累或耗尽偏置下实现高频性能。每个MOS电容器的顶部导体电耦合到另一个MOS电容器的连接并与逻辑晶体管阱一致地偏置。 MOS电容器的结合和/或高剂量植入物在其掺杂剂极性方面表现出不对称性。

5. 发明授权

US08227846B2 Systems and methods for a continuous-well decoupling capacitor 有权
标题翻译：连续井解耦电容器的系统和方法
公开(公告)号：US08227846B2
公开(公告)日：2012-07-24
申请号：US12705185
申请日：2010-02-12
申请人： Andrew E. Carlson
发明人： Andrew E. Carlson
IPC分类号： H01L29/76 , H01L29/788
CPC分类号： H01L29/94 , H01L27/0805 , H01L27/0811
摘要： A decoupling capacitor includes a pair of MOS capacitors formed in wells of opposite plurality. Each MOS capacitor has a set of well-ties and a high-dose implant, allowing high frequency performance under accumulation or depletion biasing. The top conductor of each MOS capacitor is electrically coupled to the well-ties of the other MOS capacitor and biased consistently with logic transistor wells. The well-ties and/or the high-dose implants of the MOS capacitors exhibit asymmetry with respect to their dopant polarities.
摘要翻译：去耦电容器包括形成在相反多个孔中的一对MOS电容器。每个MOS电容器具有一系列的适应性和高剂量的植入物，可以在积累或耗尽偏置下实现高频性能。每个MOS电容器的顶部导体电耦合到另一个MOS电容器的连接并与逻辑晶体管阱一致地偏置。 MOS电容器的结合和/或高剂量植入物在其掺杂剂极性方面表现出不对称性。

6. 发明申请

US20110049635A1 HANDSHAKE STRUCTURE FOR IMPROVING LAYOUT DENSITY 有权
标题翻译：用于改善布局密度的汉斯克结构
公开(公告)号：US20110049635A1
公开(公告)日：2011-03-03
申请号：US12551019
申请日：2009-08-31
申请人： Andrew E. Carlson
发明人： Andrew E. Carlson
IPC分类号： H01L27/088 , H01L21/28
CPC分类号： H01L27/0207 , H01L21/76895 , H01L21/823456 , H01L21/823475 , H01L23/485 , H01L27/088 , H01L29/4238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a gate on a semiconductor substrate. One side wall of the gate may include at least one protrusion and an opposite side wall of the gate may include at least one depression. A contact is formed through an insulating layer disposed over the gate. The contact at least partially overlaps at least one of the protrusions in the gate. A metal layer is disposed on the insulating layer. The metal layer includes a first structure shifted to a first side of the gate. The first structure at least partially overlaps the contact such that the contact electrically couples the first structure to the gate through the insulating layer.
摘要翻译：半导体器件包括半导体衬底上的栅极。门的一个侧壁可以包括至少一个突起，并且门的相对的侧壁可以包括至少一个凹陷。通过设置在栅极上方的绝缘层形成接触。接触件至少部分地与栅极中的至少一个突起重叠。金属层设置在绝缘层上。金属层包括偏移到栅极的第一侧的第一结构。第一结构至少部分地重叠接触，使得接触件通过绝缘层将第一结构电耦合到栅极。

7. 发明授权

US08101481B1 Spacer lithography processes 有权
标题翻译：间隔光刻工艺
公开(公告)号：US08101481B1
公开(公告)日：2012-01-24
申请号：US12036836
申请日：2008-02-25
申请人： Andrew E. Carlson
发明人： Andrew E. Carlson
IPC分类号： H01L21/8234
CPC分类号： H01L27/1104 , H01L21/0337 , H01L21/0338 , H01L21/28132 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/32139 , H01L21/76283 , H01L21/76816 , H01L21/76895 , H01L21/823437 , H01L21/823468 , H01L21/823481 , H01L21/84
摘要： A spacer lithography process for creating negative features such as, for example, cut-lines, or trenches, and holes is provided. The negative spacer lithography process may be utilized along with positive spacer lithography to fabricate electronic devices or the like. In one embodiment, a process is provided for fabricating a 6-transistor Static Random-Access Memory (SRAM) cell or arrays of 6-transistor SRAM cells using only, or at least primarily, positive and negative spacer lithography.
摘要翻译：提供了用于产生诸如切割线或沟槽和孔的负面特征的间隔光刻工艺。负间隔光刻工艺可以与正间隔光刻一起使用以制造电子器件等。在一个实施例中，提供了用于仅使用或至少主要为正和负间隔光刻制造6晶体管静态随机存取存储器（SRAM）单元或6晶体管SRAM单元的阵列的过程。

8. 发明授权

US07804317B1 Test device for determining charge damage to a transistor 有权
标题翻译：用于确定对晶体管的电荷损坏的测试装置
公开(公告)号：US07804317B1
公开(公告)日：2010-09-28
申请号：US11583758
申请日：2006-10-19
申请人： Biju Parameshwaran , Sriram Madhavan , Andrew E. Carlson
发明人： Biju Parameshwaran , Sriram Madhavan , Andrew E. Carlson
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , H01L22/34
摘要： According to one exemplary embodiment, a test device includes a transistor situated on a substrate. The test device further includes a protection device coupled by a fuse to a gate of the transistor in an interconnect metal layer, where the interconnect metal layer is formed over the substrate. The fuse allows the protection device to be decoupled from the gate of the transistor prior to testing the transistor. The test device further includes first and second contact pads formed over the substrate and coupled to respective terminals of the fuse to provide access to the fuse. A current can be applied between the first and second contacts pads to cause the fuse to open to decouple the protection device from the gate of the transistor. The test device further includes an antenna coupled to the gate of the transistor with interconnect metal segments for accumulating electrical charge during wafer processing.
摘要翻译：根据一个示例性实施例，测试装置包括位于基板上的晶体管。测试装置还包括保护装置，其通过熔丝耦合到互连金属层中的晶体管的栅极，其中互连金属层形成在衬底上。熔丝允许保护器件在测试晶体管之前与晶体管的栅极分离。测试装置还包括形成在衬底上的第一和第二接触焊盘，并且耦合到熔丝的相应端子以提供对熔丝的接触。可以在第一和第二接触焊盘之间施加电流以使保险丝断开以将保护装置与晶体管的栅极分离。测试装置还包括天线，其耦合到具有用于在晶片处理期间累积电荷的互连金属段的晶体管的栅极。

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