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1. 发明申请

US20120027214A1 KEY IMPLEMENTATION SYSTEM 有权
标题翻译：关键实施系统
公开(公告)号：US20120027214A1
公开(公告)日：2012-02-02
申请号：US13253591
申请日：2011-10-05
申请人： Kaoru YOKOTA , Akihito Katsura , Yusuke Nemoto , Yuishi Torisaki , Makoto Fujiwara
发明人： Kaoru YOKOTA , Akihito Katsura , Yusuke Nemoto , Yuishi Torisaki , Makoto Fujiwara
IPC分类号： H04L9/00
CPC分类号： H04L9/0866 , G06F21/10 , G06F21/556 , G06F21/72 , G06F2221/0797 , H04L9/0822 , H04L9/0897 , H04L9/321 , H04L63/0428 , H04L63/06 , H04L63/10 , H04L2209/605 , H04L2463/101
摘要： An LSI includes a first decryptor which receives first encrypted key data, and decrypts the first encrypted key data using a first cryptographic key, thereby generating first decrypted key data, a second cryptographic key generator which generates a second cryptographic key based on a second ID, a second encryptor which encrypts the first decrypted key data using the second cryptographic key, thereby generating second encrypted key data, and a second decryptor which decrypts the second encrypted key data using the second cryptographic key, thereby generating second decrypted key data. At a time of key setting, the second encryptor stores the second encrypted key data in a storage unit. At a time of key usage, the second decryptor reads the second encrypted key data from the storage unit.
摘要翻译： LSI包括：第一解密器，其接收第一加密密钥数据，并使用第一加密密钥对第一加密密钥数据进行解密，从而生成第一解密密钥数据;第二加密密钥生成器，其基于第二ID生成第二加密密钥; 第二加密器，其使用所述第二加密密钥对所述第一解密密钥数据进行加密，从而生成第二加密密钥数据;以及第二解密器，其使用所述第二加密密钥对所述第二加密密钥数据进行解密，从而生成第二解密密钥数据。在密钥设置时，第二加密器将第二加密密钥数据存储在存储单元中。在密钥使用时，第二解密器从存储单元读取第二加密密钥数据。

2. 发明授权

US07002253B2 Semiconductor device and design method thereof 失效
标题翻译：半导体器件及其设计方法
公开(公告)号：US07002253B2
公开(公告)日：2006-02-21
申请号：US10832245
申请日：2004-04-27
申请人： Akihito Katsura , Hiroo Yamamoto
发明人： Akihito Katsura , Hiroo Yamamoto
IPC分类号： H01L23/52
CPC分类号： H01L23/5225 , H01L2924/0002 , H01L2924/00
摘要： It is an object of the present invention to achieve a semiconductor device capable of preventing circuit malfunctions caused by noise without decreasing an integration degree of the circuit by making a space between signal interconnections wider and inserting a shield or a shield layer between the signal interconnections. The semiconductor device has a multilayer interconnection structure wherein three or more interconnection layers are stacked on a silicon semiconductor substrate, and comprises: a first signal line which is formed with a (N−1)-th interconnection layer and comprises a latch circuit; a second signal line which is formed with a (N+1)-th interconnection layer and is arranged so as to cross the first signal line or partially overlap thereover; and a power supply interconnection serving as a shield interconnection which is formed with an N-th interconnection layer in a portion directly beneath the first signal line and the second signal line.
摘要翻译：本发明的目的是实现一种半导体器件，其能够通过使信号互连之间的间隔较宽并在信号互连之间插入屏蔽层或屏蔽层，从而防止由噪声引起的电路故障而不降低电路的积分度。半导体器件具有多层互连结构，其中三个或更多个互连层堆叠在硅半导体衬底上，并且包括：形成有第（N-1）布线层并包括锁存电路的第一信号线; 第二信号线，其形成有第（N + 1）个互连层，并且被布置成与第一信号线交叉或部分地与其重叠; 以及用作屏蔽互连的电源互连，其在第一信号线和第二信号线正下方的部分中形成有第N互连层。

3. 发明授权

US08787582B2 Key implementation system 有权
标题翻译：关键实施制度
公开(公告)号：US08787582B2
公开(公告)日：2014-07-22
申请号：US13253591
申请日：2011-10-05
申请人： Kaoru Yokota , Akihito Katsura , Yusuke Nemoto , Yuishi Torisaki , Makoto Fujiwara
发明人： Kaoru Yokota , Akihito Katsura , Yusuke Nemoto , Yuishi Torisaki , Makoto Fujiwara
IPC分类号： H04L9/08
CPC分类号： H04L9/0866 , G06F21/10 , G06F21/556 , G06F21/72 , G06F2221/0797 , H04L9/0822 , H04L9/0897 , H04L9/321 , H04L63/0428 , H04L63/06 , H04L63/10 , H04L2209/605 , H04L2463/101
摘要： An LSI includes a first decryptor which receives first encrypted key data, and decrypts the first encrypted key data using a first cryptographic key, thereby generating first decrypted key data, a second cryptographic key generator which generates a second cryptographic key based on a second ID, a second encryptor which encrypts the first decrypted key data using the second cryptographic key, thereby generating second encrypted key data, and a second decryptor which decrypts the second encrypted key data using the second cryptographic key, thereby generating second decrypted key data. At a time of key setting, the second encryptor stores the second encrypted key data in a storage unit. At a time of key usage, the second decryptor reads the second encrypted key data from the storage unit.
摘要翻译： LSI包括：第一解密器，其接收第一加密密钥数据，并使用第一加密密钥对第一加密密钥数据进行解密，从而生成第一解密密钥数据;第二加密密钥生成器，其基于第二ID生成第二加密密钥; 第二加密器，其使用所述第二加密密钥对所述第一解密密钥数据进行加密，从而生成第二加密密钥数据;以及第二解密器，其使用所述第二加密密钥对所述第二加密密钥数据进行解密，从而生成第二解密密钥数据。在密钥设置时，第二加密器将第二加密密钥数据存储在存储单元中。在密钥使用时，第二解密器从存储单元读取第二加密密钥数据。

4. 发明申请

US20100156462A1 PROGRAMMABLE LOGIC ARRAY AND PROGRAMMABLE LOGIC ARRAY MODULE GENERATOR 审中-公开
标题翻译：可编程逻辑阵列和可编程逻辑阵列模块发电机
公开(公告)号：US20100156462A1
公开(公告)日：2010-06-24
申请号：US11997644
申请日：2006-08-01
申请人： Akihito Katsura
发明人： Akihito Katsura
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/1778 , H03K19/17784
摘要： A PLA contains an input plane (10) including a plurality of data lines (103) and a plurality of product term lines (104) having voltage levels changed in accordance with signal input to the plurality of data lines; and an output plane (20) including a plurality of product term lines (204) having voltage levels changed in accordance with the change of the voltage levels of the plurality of product term lines of the input plane and a plurality of data lines (203) for outputting signals in accordance with the voltage levels of the plurality of product term lines. In this PLA, at least one of the data lines of at least one of the input plane and the output plane has data terminals (101) at both ends thereof.
摘要翻译： PLA包括输入平面（10），包括多个数据线（103）和具有根据输入到多条数据线的信号而变化的电压电平的多个乘积项线（104）以及输出平面（20），包括多个产品项线（204），其具有根据输入平面的多个乘积项线和多个数据线（203）的电压电平的变化而变化的电压电平，用于根据多个产品项线的电压电平输出信号。在该PLA中，输入面和输出面中的至少一方的至少一条数据线在其两端具有数据端子（101）。

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