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1. 发明申请

US20060156091A1 Methods and apparatus for testing a memory 有权
公开(公告)号：US20060156091A1
公开(公告)日：2006-07-13
申请号：US11023677
申请日：2004-12-28
申请人： Anthony Aipperspach , Louis Bushard , Akihiko Fukui , Garrett Koch
发明人： Anthony Aipperspach , Louis Bushard , Akihiko Fukui , Garrett Koch
IPC分类号： G11C29/00
CPC分类号： G11C29/32 , G11C29/16 , G11C2029/3202
摘要： In a first aspect, a first method is provided that includes the steps of (1) transmitting a first signal representative of a test operation from a test circuit to a memory via a first signal path; (2) transmitting a second signal, synchronized with the first signal, from the test circuit to the memory via a second signal path; and (3) initiating the test operation on the memory in response to the second signal arriving at the memory. Numerous other aspects are provided.

2. 发明申请

US20110075494A1 DATA TRANSFER CIRCUIT 失效
标题翻译：数据传输电路
公开(公告)号：US20110075494A1
公开(公告)日：2011-03-31
申请号：US12888682
申请日：2010-09-23
申请人： Akihiko Fukui , Naoki Kiryu
发明人： Akihiko Fukui , Naoki Kiryu
IPC分类号： G11C7/10 , G11C8/18
CPC分类号： G11C29/14 , G01R31/318541 , G01R31/318594 , G11C29/023 , G11C29/12015 , G11C2029/3202
摘要： A data transfer circuit includes: an asynchronous memory to which transfer data is written from a first clock domain with a first clock and from which the written transfer data is read to a second clock domain with a second clock; a scan flip-flop whose input terminal is connected to a first position located on a data path, of the transfer data, from the asynchronous memory to the second clock domain, and whose output terminal is connected to a second position located on a data path, of the transfer data, from the asynchronous memory to the first position; and a clock selector which selects a clock to drive the scan flip-flop from the first clock and the second clock.
摘要翻译：数据传输电路包括：异步存储器，用第一时钟从第一时钟域写入传输数据，并且用第二时钟将写入的传输数据从其读取到第二时钟域; 扫描触发器，其输入端子连接到位于数据路径上的传输数据的第一位置，从异步存储器连接到第二时钟域，并且其输出端子连接到位于数据路径上的第二位置的传输数据，从异步存储器到第一位置; 以及时钟选择器，其从第一时钟和第二时钟选择时钟来驱动扫描触发器。

3. 发明授权

US08130570B2 Data transfer circuit 失效
标题翻译：数据传输电路
公开(公告)号：US08130570B2
公开(公告)日：2012-03-06
申请号：US12888682
申请日：2010-09-23
申请人： Akihiko Fukui , Naoki Kiryu
发明人： Akihiko Fukui , Naoki Kiryu
IPC分类号： G11C7/10
CPC分类号： G11C29/14 , G01R31/318541 , G01R31/318594 , G11C29/023 , G11C29/12015 , G11C2029/3202
摘要： A data transfer circuit includes: an asynchronous memory to which transfer data is written from a first clock domain with a first clock and from which the written transfer data is read to a second clock domain with a second clock; a scan flip-flop whose input terminal is connected to a first position located on a data path, of the transfer data, from the asynchronous memory to the second clock domain, and whose output terminal is connected to a second position located on a data path, of the transfer data, from the asynchronous memory to the first position; and a clock selector which selects a clock to drive the scan flip-flop from the first clock and the second clock.
摘要翻译：数据传输电路包括：异步存储器，用第一时钟从第一时钟域写入传输数据，并且用第二时钟将写入的传输数据从其读取到第二时钟域; 扫描触发器，其输入端子连接到位于数据路径上的传输数据的第一位置，从异步存储器连接到第二时钟域，并且其输出端子连接到位于数据路径上的第二位置的传输数据，从异步存储器到第一位置; 以及时钟选择器，其从第一时钟和第二时钟选择时钟来驱动扫描触发器。

4. 发明授权

US07562267B2 Methods and apparatus for testing a memory 有权
标题翻译：用于测试记忆体的方法和装置
公开(公告)号：US07562267B2
公开(公告)日：2009-07-14
申请号：US11023677
申请日：2004-12-28
申请人： Anthony G. Aipperspach , Louis B. Bushard , Akihiko Fukui , Garrett S. Koch
发明人： Anthony G. Aipperspach , Louis B. Bushard , Akihiko Fukui , Garrett S. Koch
IPC分类号： G01R31/28
CPC分类号： G11C29/32 , G11C29/16 , G11C2029/3202
摘要： In a first aspect, a first method is provided that includes the steps of (1) transmitting a first signal representative of a test operation from a test circuit to a memory via a first signal path; (2) transmitting a second signal, synchronized with the first signal, from the test circuit to the memory via a second signal path; and (3) initiating the test operation on the memory in response to the second signal arriving at the memory. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种第一方法，其包括以下步骤：（1）经由第一信号路径将表示测试操作的第一信号从测试电路发送到存储器; （2）经由第二信号路径将与第一信号同步的第二信号从测试电路发送到存储器; 和（3）响应于到达存储器的第二信号，在存储器上启动测试操作。提供了许多其他方面。

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