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1. 发明授权

US07214630B1 PMOS transistor with compressive dielectric capping layer 有权
标题翻译：具有压电绝缘覆盖层的PMOS晶体管
公开(公告)号：US07214630B1
公开(公告)日：2007-05-08
申请号：US11124443
申请日：2005-05-06
申请人： Bhadri N. Varadarajan , James S. Sims , Akhil Singhal
发明人： Bhadri N. Varadarajan , James S. Sims , Akhil Singhal
IPC分类号： H01L21/31
CPC分类号： H01L21/3185 , C23C16/30 , C23C16/56 , H01L21/3105 , H01L21/3148 , H01L29/665 , H01L29/78 , H01L29/7843
摘要： A salicide layer is deposited on the source/drain regions of a PMOS transistor. A dielectric capping layer having residual compressive stress is formed on the salicide layer by depositing a plurality of PECVD dielectric sublayers and plasma-treating each sublayer. Compressive stress from the dielectric capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in the PMOS channel. To form a compressive dielectric layer, a deposition reactant mixture containing A1 atoms and A2 atoms is provided in a vacuum chamber. Element A2 is more electronegative than element A1, and A1 atoms have a positive oxidation state and A2 atoms have a negative oxidation state when A1 atoms are bonded with A2 atoms. A deposition plasma is generated by applying HF and LF radio-frequency power to the deposition reactant mixture, and a sublayer of compressive dielectric material is deposited. A post-treatment plasma is generated by applying HF and LF radio-frequency power to a post-treatment gas that does not contain at least one of A1 atoms and A2 atoms. Compressive stress in the dielectric sublayer is increased by treating the sublayer in the post-treatment plasma. Processes of depositing a dielectric sublayer and post-treating the sublayer in plasma are repeated until a desired thickness is achieved. The resulting dielectric layer has residual compressive stress.
摘要翻译：硅化物层沉积在PMOS晶体管的源/漏区上。通过沉积多个PECVD电介质子层并对每个子层进行等离子体处理，在自对准硅层上形成具有残余压应力的电介质覆盖层。来自介电覆盖层的压缩应力通过源极 - 漏极区域单向转移到PMOS沟道，以在PMOS沟道中产生压缩应变。为了形成压电介质层，在真空室中提供含有A1原子和A2原子的沉积反应物混合物。元素A2比元素A1更负电，A1原子具有正的氧化态，当A2原子与A2原子键合时，A2原子具有负的氧化态。通过对沉积反应物混合物施加HF和LF射频功率来产生沉积等离子体，并且沉积压电介质材料的子层。通过对不包含A1原子和A2原子中的至少一个的后处理气体施加HF和LF射频功率来产生后处理等离子体。通过处理后处理等离子体中的子层来增加介电层中的压缩应力。重复沉积介电子层并对等离子体中的子层进行后处理的工艺，直到实现所需的厚度。所得到的介电层具有残余压应力。

2. 发明授权

US07327001B1 PMOS transistor with compressive dielectric capping layer 有权
标题翻译：具有压电绝缘覆盖层的PMOS晶体管
公开(公告)号：US07327001B1
公开(公告)日：2008-02-05
申请号：US11731265
申请日：2007-03-29
申请人： Akhil Singhal , James S. Sims , Bhadri N. Varadarajan
发明人： Akhil Singhal , James S. Sims , Bhadri N. Varadarajan
IPC分类号： H01L29/76
CPC分类号： H01L21/3185 , C23C16/30 , C23C16/56 , H01L21/3105 , H01L21/3148 , H01L29/665 , H01L29/78 , H01L29/7843
摘要： A salicide layer is deposited on the source/drain regions of a PMOS transistor. A dielectric capping layer having residual compressive stress is formed on the salicide layer by depositing a plurality of PECVD dielectric sublayers and plasma-treating each sublayer. Compressive stress from the dielectric capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in the PMOS channel. To form a compressive dielectric layer, a deposition reactant mixture containing A1 atoms and A2 atoms is provided in a vacuum chamber. Element A2 is more electronegative than element A1, and A1 atoms have a positive oxidation state and A2 atoms have a negative oxidation state when A1 atoms are bonded with A2 atoms. A deposition plasma is generated by applying HF and LF radio-frequency power to the deposition reactant mixture, and a sublayer of compressive dielectric material is deposited. A post-treatment plasma is generated by applying HF and LF radio-frequency power to a post-treatment gas that does not contain at least one of A1 atoms and A2 atoms. Compressive stress in the dielectric sublayer is increased by treating the sublayer in the post-treatment plasma. Processes of depositing a dielectric sublayer and post-treating the sublayer in plasma are repeated until a desired thickness is achieved. The resulting dielectric layer has residual compressive stress.
摘要翻译：硅化物层沉积在PMOS晶体管的源/漏区上。通过沉积多个PECVD电介质子层并对每个子层进行等离子体处理，在自对准硅层上形成具有残余压应力的电介质覆盖层。来自介电覆盖层的压缩应力通过源极 - 漏极区域单向转移到PMOS沟道，以在PMOS沟道中产生压缩应变。为了形成压电介质层，在真空室中提供含有A1原子和A2原子的沉积反应物混合物。元素A2比元素A1更负电，A1原子具有正的氧化态，当A2原子与A2原子键合时，A2原子具有负的氧化态。通过对沉积反应物混合物施加HF和LF射频功率来产生沉积等离子体，并且沉积压电介质材料的子层。通过对不包含A1原子和A2原子中的至少一个的后处理气体施加HF和LF射频功率来产生后处理等离子体。通过处理后处理等离子体中的子层来增加介电层中的压缩应力。重复沉积介电子层并对等离子体中的子层进行后处理的工艺，直到实现所需的厚度。所得到的介电层具有残余压应力。

3. 发明授权

US07998881B1 Method for making high stress boron-doped carbon films 有权
标题翻译：制备高应力硼掺杂碳膜的方法
公开(公告)号：US07998881B1
公开(公告)日：2011-08-16
申请号：US12134961
申请日：2008-06-06
申请人： Qingguo Wu , James S. Sims , Mandyam Sriram , Seshasayee Varadarajan , Akhil Singhal
发明人： Qingguo Wu , James S. Sims , Mandyam Sriram , Seshasayee Varadarajan , Akhil Singhal
IPC分类号： H01L21/469
CPC分类号： H01L21/76834 , H01L21/02115 , H01L21/02274 , H01L21/823807 , H01L29/665 , H01L29/7843
摘要： Transistor architectures and fabrication processes generate channel strain without adversely impacting the efficiency of the transistor fabrication process while preserving the material quality and enhancing the performance of the resulting transistor. Transistor strain is generated is PMOS devices using a highly compressive post-salicide boron doped carbon capping layer applied as a blanket over on at least the source and drain regions. The stress from this capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in PMOS channel.
摘要翻译：晶体管架构和制造工艺产生通道应变，而不会不利地影响晶体管制造工艺的效率，同时保持材料质量并增强所得晶体管的性能。产生晶体管应变是使用在至少源极和漏极区上作为覆盖层施加的高度压缩的后硅化物硼掺杂碳覆盖层的PMOS器件。来自该覆盖层的应力通过源极 - 漏极区域单轴转移到PMOS沟道，以在PMOS沟道中产生压缩应变。

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