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1. 发明申请

US20070243714A1 Method of controlling silicon-containing polymer build up during etching by using a periodic cleaning step 审中-公开
标题翻译：通过使用周期性清洁步骤在蚀刻期间控制含硅聚合物积累的方法
公开(公告)号：US20070243714A1
公开(公告)日：2007-10-18
申请号：US11406000
申请日：2006-04-18
申请人： Taeho Shin , Jingbao Liu , Ajey Joshi , Jong Kim , Wei-Te Wu
发明人： Taeho Shin , Jingbao Liu , Ajey Joshi , Jong Kim , Wei-Te Wu
IPC分类号： H01L21/461 , C03C15/00
CPC分类号： H01L21/76802 , H01L21/31122 , H01L21/31144
摘要： A method of removing a silicon-containing hard polymeric material from an opening leading to a recessed feature during the plasma etching of said recessed feature into a carbon-containing layer in a semiconductor substrate. The method comprises the intermittent use of a cleaning step within a continuous etching process, where at least one fluorine-containing cleaning agent species is added to already present etchant species of said continuous etching process for a limited time period, wherein the length of time of each cleaning step ranges from about 5% to about 100% of the time length of an etch step which either precedes or follows said cleaning step.
摘要翻译：在将所述凹入特征等离子体蚀刻到半导体衬底中的含碳层中时，从导通凹陷特征的开口去除含硅的硬质聚合物材料的方法。该方法包括在连续蚀刻过程中间歇地使用清洁步骤，其中在有限时间段内将至少一种含氟清洁剂种类添加到已存在的所述连续蚀刻工艺的蚀刻剂物质中，其中时间长度每个清洁步骤的范围是在所述清洁步骤之前或之后的蚀刻步骤的时间长度的约5％至约100％。

2. 发明申请

US20060051968A1 Self-aligned contact etch with high sensitivity to nitride shoulder 审中-公开
标题翻译：自对准接触蚀刻，对氮化物肩部具有高灵敏度
公开(公告)号：US20060051968A1
公开(公告)日：2006-03-09
申请号：US10498857
申请日：2002-12-12
申请人： Ajey Joshi , Pui Man Ng , James Stinnett , Usama Dadu , Jason Regis
发明人： Ajey Joshi , Pui Man Ng , James Stinnett , Usama Dadu , Jason Regis
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/76897 , H01J37/3266 , H01L21/31116
摘要： A method and apparatus are provided for etching semiconductor and dielectric substrates through the use of plasmas based on mixtures of a first gas having the formula CaFb, and a second gas having the formula CxHyFz, wherein a/b≧⅔, and wherein x/z≧½. The mixtures may be used in low or medium density plasmas sustained in a magnetically enhanced reactive ion chamber to provide a process that exhibits excellent corner layer selectivity, photo resist selectivity, under layer selectivity, and profile and bottom CD control. The percentages of the first and second gas may be varied during etching to provide a plasma that etches undoped oxide films or to provide an etch stop on such films.
摘要翻译：提供了一种方法和装置，用于通过使用等离子体来蚀刻半导体和电介质基底，所述等离子体基于具有式C a B b B b的第一气体的混合物和第二气体其中a / b> = 2/3，并且其中x / z> = 1/2。混合物可以用于在磁增强反应离子室中维持的低或中等密度等离子体，以提供显示出优异的角层选择性，光致抗蚀剂选择性，底层选择性以及轮廓和底部CD控制的方法。在蚀刻期间可以改变第一和第二气体的百分比，以提供蚀刻未掺杂的氧化物膜的等离子体或在这种膜上提供蚀刻停止。

3. 发明授权

US5952896A Impedance matching network 失效
标题翻译：阻抗匹配网络
公开(公告)号：US5952896A
公开(公告)日：1999-09-14
申请号：US954376
申请日：1997-10-20
申请人： Richard R. Mett , Robert D. Greenway , Gabriel Bilek , Ajey Joshi
发明人： Richard R. Mett , Robert D. Greenway , Gabriel Bilek , Ajey Joshi
IPC分类号： H01F21/04 , H01F21/10 , H03H7/38
CPC分类号： H03H7/38
摘要： A high efficiency radio frequency (RF) impedance matching network containing an "L-type" inductor-capacitor (LC) circuit where the capacitor is a variable capacitor coupled from an input port to ground and the inductor is a variable inductance inductor coupled from the input port to an output port. A blocking capacitor is provided between the inductor and the output port and a ceramic capacitor is coupled in parallel across the variable capacitor. The impedance match is tuned by physically adjusting tuning elements of both the inductor and capacitor. The variable inductor contains an improved inductor tuning element that optimizes current flow in the tuning elements and inductor. To further improve the efficiency of the matching network, the assembly uses an improved enclosure interior finish and various circuit optimization techniques that reduce contributions to match loop resistance.
摘要翻译：包含“L型”电感器 - 电容器（LC）电路的高效率射频（RF）阻抗匹配网络，其中电容器是从输入端口耦合到地的可变电容器，并且电感器是从输入端口到输出端口。在电感器和输出端口之间提供隔离电容器，并且陶瓷电容器并联在可变电容器上。通过物理调节电感和电容的调谐元件来调整阻抗匹配。可变电感器包含改进的电感调谐元件，优化调谐元件和电感器中的电流。为了进一步提高匹配网络的效率，该组件使用改进的外壳内部表面处理和各种电路优化技术，减少对匹配环路电阻的贡献。

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