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1. 发明专利

JP2004146836A Circuit substrate and method for manufacturing the same 审中-公开
公开(公告)号：JP2004146836A
公开(公告)日：2004-05-20
申请号：JP2003363830
申请日：2003-10-23
申请人： Advanced Semiconductor Engineering Inc , Ase Material Inc , 日月光半導體製造股▲分▼有限公司 , 日月宏科技股▲分▼有限公司
发明人： OU IN-DE , HUNG CHIH-PIN , CHEN CHIA-SHANG , LIN KUANG-HUA , CHAO SHIN-HUA
IPC分类号： H05K3/28 , H01L23/498 , H05K1/11 , H05K3/04 , H05K3/40 , H05K3/42 , H05K3/46
CPC分类号： H01L23/49827 , H01L2924/0002 , H05K1/115 , H05K3/043 , H05K3/403 , H05K3/429 , H05K2201/09509 , H05K2201/09536 , H05K2201/0959 , H05K2201/09645 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a circuit substrate and a method for manufacturing the same, in which the wire density is increased, and the signal transfer path is reduced without reducing the wire diameter or the pitches of the conductive traces. SOLUTION: The circuit board 400 comprises a base material, a hole 440, metal layers 450a and 450b, and an insulator 480. The base material is composed of a core material 401 and a plurality of insulating layers 410 and a plurality of conductive trace layers 430 alternately laminated. The metal layers 450a and 450b are formed on the sidewall of the hole 440 and surround the inner wall surface of the hole 440. Lands 460a and 460b surround the circumferential edge of the hole 440. The insulator 480 is filled in the hole 440, and at the same time, divides the hole 440 into two parts. The metal layers 450a and 450b and the lands 460a and 460b are electrically insulated from each other with the insulator 480, and the metal layers 450a and 450b are electrically connected to the conductive trace, in the conductive trace layer 430 via the lands 460a and 460b, respectively. COPYRIGHT: (C)2004,JPO

2. 发明专利

JP2006184170A Contact sensor package structure 审中-公开
标题翻译：联系传感器包装结构
公开(公告)号：JP2006184170A
公开(公告)日：2006-07-13
申请号：JP2004379389
申请日：2004-12-28
申请人： Advanced Semiconductor Engineering Inc , 日月光半導體製造股▲分▼有限公司
发明人： LEE SHIH-CHANG , LEE CHENG-YIN , LU YUNG-LI , YEH YING-TSAI , LIN PEI-CHI
IPC分类号： G01B7/28
摘要： PROBLEM TO BE SOLVED: To provide a contact sensor package structure capable of reducing a problem of electrostatic charges by discharging the electrostatic charges.
SOLUTION: This contact sensor package structure has a substrate, a film, a sealant, and a plurality of contact sensors arranged on the substrate. The contact sensors are arranged in a sealed space defined by the substrate, the film and the sealant. The contact sensor package structure also has an earthed conductive trace formed on the substrate, and an electrostatic charge discharge layer formed on the surface of the film and connected electrically to the earthed conductive trace. The electrostatic charge discharge layer has an upper surface functioning as a contact surface for detecting a contact workpiece.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供能够通过排出静电电荷来减少静电电荷的问题的接触传感器封装结构。解决方案：该接触传感器封装结构具有衬底，膜，密封剂和布置在衬底上的多个接触传感器。接触传感器布置在由基底，膜和密封剂限定的密封空间中。接触传感器封装结构还具有形成在衬底上的接地导电迹线，以及形成在膜的表面上并与电极接地的导电迹线相连接的静电电荷放电层。静电电荷放电层具有用作检测接触工件的接触面的上表面。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2006010676A Re-test method of semiconductor device 有权
标题翻译：半导体器件的测试方法
公开(公告)号：JP2006010676A
公开(公告)日：2006-01-12
申请号：JP2005088453
申请日：2005-03-25
申请人： Advanced Semiconductor Engineering Inc , 日月光半導体製造股▲ふん▼有限公司
发明人： CHUAN CHIN-CHEN , LIN CHIU-CHENG , LEE CHENG CHIEH , HUANG KUEI LIN , CHEN YONG LIANG , WANG JUI LIANG , CHIEN PAO TA , KUNG HSIANG-HAN , HWU CHAO HSIUNG
IPC分类号： G01R31/26 , G01R31/28 , H01L21/66
CPC分类号： G01R31/2893
摘要： PROBLEM TO BE SOLVED: To extract and test a semiconductor device put on a carrier again. SOLUTION: (1) A first semiconductor device carrier supporting a plurality of semiconductor devices after the test is provided. (2) A reserving device extracts the semiconductor device from the first semiconductor device carrier, and put it on a film frame based on the information of a first map having the information including a positional coordinate to be arranged. (3) The film frame is put on a test device, and the test device re-tests the plurality of semiconductor devices based on the information of the first map. (4) The film frame supporting the plurality of semiconductor devices is put on the reserving device. The reserving device extracts the plurality of semiconductor devices as good articles based on the re-test result of the test device, and sequentially puts them on a second semiconductor device carrier by the grade of the re-test result. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：再次提取和测试放在载体上的半导体器件。解决方案：（1）提供了在测试之后支撑多个半导体器件的第一半导体器件载体。（2）保留装置从第一半导体装置载体提取半导体装置，并且基于具有包括要布置的位置坐标的信息的第一地图的信息将其放置在胶片框上。（3）胶片框放置在测试装置上，测试装置根据第一图的信息重新测试多个半导体装置。（4）将保持多个半导体装置的胶卷框架放置在保留装置上。预留装置基于测试装置的重新测试结果将多个半导体器件提取为好的物品，并且按照再测试结果的等级将它们依次放置在第二半导体器件载体上。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2005250450A Micro-mirror package 审中-公开
标题翻译： MICRO-MIRROR包装
公开(公告)号：JP2005250450A
公开(公告)日：2005-09-15
申请号：JP2004380974
申请日：2004-12-28
申请人： Advanced Semiconductor Engineering Inc , 日月光半導體製造股▲分▼有限公司
发明人： YEE KUO-CHUNG
IPC分类号： B81B3/00 , G02B26/08 , H01L21/00 , H01L21/70
CPC分类号： G02B26/0816 , H01L2224/48091 , H01L2224/73265 , H01L2924/01019 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a micro-machine semiconductor package structure which has less thermal deformation.
SOLUTION: In a micro-mirror package 100, a first spacer 116 is embedded in a first adhesive disposed between a cover substrate and a semiconductor chip 112, sets the cover substrate and the semiconductor chip 112 apart, and installs the cover substrate to the semiconductor chip 112. A second spacer 152 is embedded in a second adhesive, disposed between the semiconductor chip 112 and the bottom substrate 150, sets them apart, and installs the semiconductor chip 112 to the bottom substrate 150. The wire 130 is used to electrically connect the semiconductor chip 112 and the substrate 120. The lid 126 is provided at the upper part of the circular wall 122.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有较少热变形的微机半导体封装结构。解决方案：在微反射镜封装100中，将第一间隔物116嵌入设置在盖基板和半导体芯片112之间的第一粘合剂中，将盖基板和半导体芯片112分开设置，并安装盖基板半导体芯片112.第二间隔件152嵌入设置在半导体芯片112和底部基板150之间的第二粘合剂中，将它们分开，并将半导体芯片112安装到底部基板150.使用导线130 电连接半导体芯片112和基板120.盖126设置在圆形壁122的上部。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2005328028A Package structure of optical device and method for manufacturing the same 有权
标题翻译：光学装置的包装结构及其制造方法
公开(公告)号：JP2005328028A
公开(公告)日：2005-11-24
申请号：JP2005029743
申请日：2005-02-04
申请人： Advanced Semiconductor Engineering Inc , 日月光半導體製造股▲分▼有限公司
发明人： YEE KUO-CHUNG
IPC分类号： H01L27/14 , H01L21/00 , H01L21/56 , H01L23/02 , H01L23/12 , H01L27/146 , H01L29/18 , H01L29/417 , H04N5/335
CPC分类号： H01L27/14618 , H01L24/97 , H01L2224/05553 , H01L2224/48091 , H01L2224/49175 , H01L2224/73265 , H01L2924/14 , H01L2924/15787 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide the package structure of an optical semiconductor integrated circuit device of which the manufacturing cost can be reduced. SOLUTION: The package structure of an optical device is provided with a chip, a sealant, a cover, a substrate, a plurality of bonding wires, and a transparent encapsulant. The chip has an optical device and a plurality of chip connection pads. The sealant is disposed around the optical device. The cover is disposed on the sealant. The substrate for supporting the chip has a plurality of connection pads. The bonding wires are used for electrically connecting the chip connection pads of the chip to the connection pads of the substrate. The transparent encapsulant is formed over the substrate and the cover to encapsulate the bonding wires. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供可以降低制造成本的光半导体集成电路器件的封装结构。解决方案：光学器件的封装结构设置有芯片，密封剂，盖，衬底，多个接合线和透明密封剂。芯片具有光学器件和多个芯片连接焊盘。密封剂设置在光学装置周围。盖子设置在密封剂上。用于支撑芯片的基板具有多个连接焊盘。接合线用于将芯片的芯片连接焊盘电连接到衬底的连接焊盘。透明密封剂形成在衬底和盖上以封装接合线。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2005167242A Warp preventing package and its manufacturing method 有权
标题翻译： WARP防护包及其制造方法
公开(公告)号：JP2005167242A
公开(公告)日：2005-06-23
申请号：JP2004344216
申请日：2004-11-29
申请人： Advanced Semiconductor Engineering Inc , 日月光半導體製造股▲ふん▼有限公司
发明人： YEE KUO-CHUNG
IPC分类号： H01L23/29 , H01L21/48 , H01L21/50 , H01L21/56 , H01L23/16 , H01L23/28 , H01L23/31
CPC分类号： H01L21/565 , H01L23/16 , H01L23/3121 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a warp preventing package comprising a packaging substrate, a chip and a structural reinforcement.
SOLUTION: There is provided the warp preventing package, wherein the chip is arranged at a top face of the packaging substrate, and the structural reinforcement is arranged at a position just under a region surrounding the chip at a lower surface side of the packaging substrate, and by arranging the structural reinforcement like this, at the time of encapsulating the chip in a molding compound, a force to warp the packaging substrate is counterbalanced.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供包括包装基板，芯片和结构加强件的防翘曲包装。解决方案：提供了防翘曲包装，其中芯片布置在包装基板的顶面，并且结构加强件布置在位于包装基板的下表面侧的芯片附近的位置的位置处包装基板，并且通过设置这样的结构加强件，在将芯片封装在模塑料中时，使包装基板翘曲的力被抵消。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2005197717A Structure of image sensor package and its forming method, and structure of optical element package and its forming method 审中-公开
标题翻译：图像传感器封装结构及其形成方法，光学元件封装结构及其形成方法
公开(公告)号：JP2005197717A
公开(公告)日：2005-07-21
申请号：JP2004378632
申请日：2004-12-28
申请人： Advanced Semiconductor Engineering Inc , 日月光半導體製造股▲分▼有限公司
发明人： YEE KUO-CHUNG
IPC分类号： H01L27/14 , H01L31/0203 , H01L31/0232 , H04N5/335 , H04N5/372 , H04N5/374
CPC分类号： H01L31/0203 , H01L27/14618 , H01L27/14625 , H01L27/14687 , H01L31/02325 , H01L2224/32013 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a structure of an image sensor package in which entire height is low.
SOLUTION: The image sensor package comprises a substrate, a chip, a transparent cover and a lens module. The substrate has an upper surface, a lower surface, and a plurality of connecting pad and through hole which are arranged on the lower surface. The chip has an activity surface and the image sensor arranged on the activity surface so that it may correspond to the through hole. Further, a plurality of upheaval portion are arranged on a surrounding portion of the activity surface, and electrically connected to the connecting pads. The transparent cover coats the image sensor in such a manner that it is arranged inside the pierced hole of the substrate. The lens module is arranged on the upper surface of the substrate in order to transmit light to the image sensor.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供整体高度低的图像传感器封装的结构。解决方案：图像传感器封装包括基板，芯片，透明盖和透镜模块。基板具有布置在下表面上的上表面，下表面和多个连接垫和通孔。芯片具有活动表面，并且图像传感器布置在活动表面上，使得它可以对应于通孔。此外，多个动态部分布置在活动表面的周围部分上，并且电连接到连接焊盘。透明盖以这样的方式涂覆图像传感器，使得其布置在基板的穿孔内。透镜模块布置在基板的上表面上，以将光传送到图像传感器。版权所有（C）2005，JPO＆NCIPI

8. 发明授权

US11631734B2 Vertical capacitor structure having capacitor in cavity, and method for manufacturing the vertical capacitor structure 有权
公开(公告)号：US11631734B2
公开(公告)日：2023-04-18
申请号：US17102258
申请日：2020-11-23
申请人： Advanced Semiconductor Engineering, Inc.
发明人： Syu-Tang Liu , Huang-Hsien Chang , Tsung-Tang Tsai , Hung-Jung Tu
IPC分类号： H01L49/02 , H01L21/02 , H01L23/522 , H01L21/308 , H01L21/3105 , H01L21/285
摘要： A vertical capacitor structure includes a substrate, at least a pillar, a first conductive layer, a first dielectric layer and a second conductive layer. The substrate defines a cavity. The pillar is disposed in the cavity. The first conductive layer covers and is conformal to the cavity of the substrate and the pillar, and is insulated from the substrate. The first dielectric layer covers and is conformal to the first conductive layer. The second conductive layer covers and is conformal to the first dielectric layer. The first conductive layer, the first dielectric layer and the second conductive layer jointly form a capacitor component.

9. 发明申请

US20230115954A1 ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20230115954A1
公开(公告)日：2023-04-13
申请号：US17500920
申请日：2021-10-13
申请人： Advanced Semiconductor Engineering, Inc.
发明人： En Hao HSU , Kuo Hwa TZENG , Chia-Pin CHEN , Chi Long TSAI
IPC分类号： H01L23/00 , H01L23/31 , H01L23/16
摘要： An electronic device package and manufacturing method thereof are provided. The electronic device package includes an electronic component including an active surface, a patterned conductive layer disposed on the active surface, an encapsulation layer disposed over the patterned conductive layer, and a buffer layer disposed between the patterned conductive layer and the encapsulation layer. The buffer layer is shaped and sized to alleviate a stress generated due to an interaction between the patterned conductive layer and the encapsulation layer.

10. 发明申请

US20230114278A1 SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20230114278A1
公开(公告)日：2023-04-13
申请号：US18080640
申请日：2022-12-13
申请人： Advanced Semiconductor Engineering, Inc.
发明人： Chao Wei LIU
IPC分类号： H01L23/538 , H01L23/31 , H01L21/78 , H01L21/48 , H01L21/56
摘要： A semiconductor device package and a method for manufacturing the semiconductor device package are provided. The semiconductor device package includes a first substrate, a second substrate and an interconnection. The second substrate is arranged above the first substrate and has an opening. The interconnection passes through the opening and connects to the first substrate and the second substrate.

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