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热词
    • 1. 发明授权
    • Signal processing method and apparatus for ensuring a desired relationship between signals
    • 用于确保信号之间期望的关系的信号处理方法和装置
    • US07254205B2
    • 2007-08-07
    • US10702286
    • 2003-11-06
    • Thaddeus John GabaraAdrian Patrick Lynam
    • Thaddeus John GabaraAdrian Patrick Lynam
    • H04L7/00
    • H04L7/0337H03L7/0814H03L7/091H04L7/0012
    • A signal processing circuit and method in which a given signal, e.g., a receive data clock associated with a first chip and generated by a deserializer circuit, is synchronized with another signal, e.g., a clock signal from a second chip which is asynchronous with the receive data clock. The circuit may include first, second and third processing circuits, each of which performs a sampling function on a corresponding one of an early version, a middle version and a late version of the given signal, utilizing the clock signal to which the given signal is to be synchronized. A logic circuit coupled to outputs of each of the first, second and third processing circuits generates a control signal indicative of the presence or absence of a desired relationship, e.g., a desired phase relationship, between the clock signal and the first, second and third versions of the given signal. A selection circuit, e.g., a set of multiplexers, is responsive to the control signal to alter the phase relationship between the clock signal and the first, second and third versions of the given signal if the control signal indicates the absence of the desired relationship. The logic and selection circuits may be configured as part of a feedback control loop which automatically maintains the desired relationship.
    • 一种信号处理电路和方法,其中给定信号,例如与第一芯片相关联并由解串行器电路产生的接收数据时钟与另一个信号同步,例如来自与第二芯片异步的第二芯片的时钟信号 接收数据时钟。 电路可以包括第一,第二和第三处理电路,每个处理电路使用给定信号的时钟信号,对给定信号的早期版本,中间版本和晚期版本中的相应的一个执行采样功能, 要同步 耦合到第一,第二和第三处理电路中的每一个的输出的逻辑电路产生指示在时钟信号与第一,第二和第三处理电路之间存在或不存在期望的关系(例如期望的相位关系)的控制信号 给定信号的版本。 如果控制信号指示不存在期望的关系,则选择电路(例如,一组多路复用器)响应于控制信号来改变时钟信号与给定信号的第一,第二和第三版本之间的相位关系。 逻辑和选择电路可以被配置为自动保持所需关系的反馈控制回路的一部分。