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    • 4. 发明授权
    • Power MOS transistor with equipotential ring
    • 具有等电位环的功率MOS晶体管
    • US4816882A
    • 1989-03-28
    • US138989
    • 1987-12-29
    • Richard A. BlanchardAdrian Cogan
    • Richard A. BlanchardAdrian Cogan
    • H01L21/28H01L21/331H01L21/336H01L21/60H01L29/51H01L29/78
    • H01L21/28202H01L21/76897H01L29/513H01L29/518H01L29/66333H01L29/66712H01L29/7802H01L29/511
    • A process for manufacturing a DMOS transistor in accordance with the present invention includes the steps of forming a layer of gate insulation (12, 14) on an N type substrate (10). A layer of polycrystalline silicon (16) is formed on the gate insulation layer. A first mask (18) is used to define the polycrystalline silicon gate. A layer of silicon dioxide (20) is then formed on the polycrystalline silicon gate. A second photolithographic mask (22) is formed on the wafer. The deep body region is then formed. Thereafer, portions of the gate insulation layer not covered by the polycrystalline silicon gate are removed. The P type body region (26) and N+ source region (28) are then formed having a lateral extent defined by the edge of the polycrystalline silicon gate. A conductive layer 30 l is formed on the wafer and photolithographically patterned. A passivation layer 34 is then formed on the wafer. Several types of termination are available, involving various combinations of device perimeter regions, field plates, metallized equipotential rings, and field limiting rings. Of importance, the above-described process uses only 4 photolithographic masking steps.
    • 根据本发明的制造DMOS晶体管的工艺包括在N型衬底(10)上形成栅极绝缘层(12,14)的步骤。 在栅绝缘层上形成多晶硅层(16)。 第一掩模(18)用于限定多晶硅栅极。 然后在多晶硅栅极上形成一层二氧化硅(20)。 第二光刻掩模(22)形成在晶片上。 然后形成深体区域。 此外,除去未被多晶硅栅极覆盖的栅极绝缘层的部分。 然后形成具有由多晶硅栅极的边缘限定的横向范围的P型体区域(26)和N +源极区域(28)。 导电层30l形成在晶片上并且光刻图案化。 然后在晶片上形成钝化层34。 有几种类型的端接可用,涉及器件周边区域,场板,金属化等电位环和场限制环的各种组合。 重要的是,上述过程仅使用4个光刻掩模步骤。
    • 6. 发明申请
    • Diode with improved energy impulse rating
    • 二极管具有改善的能量冲击等级
    • US20050275065A1
    • 2005-12-15
    • US10868583
    • 2004-06-14
    • Adrian CoganJiyuan LuanAdrian Mikolajczak
    • Adrian CoganJiyuan LuanAdrian Mikolajczak
    • H01L21/00H01L21/329H01L29/06H01L29/861H01L29/866
    • H01L29/0692H01L29/866
    • An energy pulse clamping semiconductor diode includes a substrate having carriers of a first type of conductivity in a first, high concentration level (e.g. n++), a first major face and a second major face opposite to the first major face; a layer of semiconductor material having carriers of the first type of conductivity in a second concentration level lower than the first level (e.g. n+), and having an outer surface; a region formed at an outer surface having carriers of a second type of conductivity in a third concentration level (e.g. p+); at least one cell having carriers of the second type of conductivity in a fourth concentration level greater than the third concentration level (e.g. p++); a cathode electrode and an anode electrode. The diode is most preferably included in an overvoltage protection circuit including a PPTC resistor in series with the cathode electrode and thermally coupled to the diode.
    • 能量脉冲钳位半导体二极管包括具有在第一高浓度水平(例如n ++),第一主面和与第一主面相对的第二主面具有第一类导电性载体的衬底; 具有低于第一水平(例如n +)的第二浓度水平的具有第一类型导电性载流子并具有外表面的半导体材料层; 形成在具有第三浓度水平(例如p +)的第二导电类型的载流子的外表面的区域; 至少一个电池具有大于第三浓度水平的第四浓度水平的第二类导电性载流子(例如p ++); 阴极电极和阳极电极。 二极管最优选地包括在包括与阴极电极串联并且与二极管耦合的PPTC电阻器的过电压保护电路中。
    • 10. 发明申请
    • Circuit protection method using diode with improved energy impulse rating
    • 使用改进的能量冲击等级的二极管的电路保护方法
    • US20070166942A1
    • 2007-07-19
    • US11724907
    • 2007-03-15
    • Adrian CoganJiyuan LuanAdrian Mikolajczak
    • Adrian CoganJiyuan LuanAdrian Mikolajczak
    • H01L21/20
    • H01L29/0692H01L29/866
    • A method for protecting a circuit from a high energy pulse includes placing a PPTC resistive element in series with the circuit and placing an energy pulse clamping semiconductor diode in shunt across the circuit and further includes forming the diode to have: a substrate with carriers of a first type of conductivity in a first, high concentration level (e.g. n++), a first major face and a second major face opposite to the first major face; a layer of semiconductor material having carriers of the first type of conductivity in a second concentration level lower than the first level (e.g. n+), and an outer surface; a region formed at an outer surface having carriers of a second type of conductivity in a third concentration level (e.g. p+); at least one cell having carriers of the second type of conductivity in a fourth concentration level greater than the third concentration level (e.g. p++); and, a cathode electrode and an anode electrode. In the method, the diode region becomes a second-level bi-directional intrinsic conduction region as an intrinsic temperature of the region is approached in response to thermal energy initially generated at the diode cell in response to the high energy electrical pulse. The method includes thermally coupling the diode to the PPTC resistive element to accelerate trip thereof in response to the high energy electrical pulse.
    • 一种用于保护电路免受高能量脉冲的方法包括将PPTC电阻元件与电路串联放置并且将能量脉冲钳位半导体二极管放置在跨越电路的并联中,还包括形成二极管以具有:具有载流子的衬底 在第一高浓度水平(例如n ++),第一主面和与第一主面相对的第二主面的第一类导电性; 具有低于第一水平(例如n +)的第二浓度水平的具有第一类型导电性的载流子的半导体材料层和外表面; 形成在具有第三浓度水平(例如p +)的第二导电类型的载流子的外表面的区域; 至少一个电池具有大于第三浓度水平的第四浓度水平的第二类导电性载流子(例如p ++); 以及阴极电极和阳极电极。 在该方法中,随着响应于高能电脉冲在二极管单元最初产生的热能而接近该区域的本征温度,二极管区域变为二级本征导通区域。 该方法包括将二极管热耦合到PPTC电阻元件,以加速其响应于高能电脉冲的跳闸。