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1. 发明申请

WO2010078643A3 METHOD AND APPARATUS FOR SILICON REFINEMENT 审中-公开
标题翻译：硅精炼方法与装置
公开(公告)号：WO2010078643A3
公开(公告)日：2010-09-16
申请号：PCT/CA2009001877
申请日：2009-12-23
申请人： ARISE TECHNOLOGIES CORP , DODD PETER , BALKOS ATHANASIOS TOM , DAWKINS JEFFREY
发明人： DODD PETER , BALKOS ATHANASIOS TOM , DAWKINS JEFFREY
IPC分类号： C01B33/039 , C01B33/037
CPC分类号： C01B33/035 , C01B33/107 , C01B33/1071 , C01B33/10715 , C01B33/10721 , C01B33/10742 , C01B33/10747 , C01B33/10757 , C01B33/10773
摘要： A method and respect material for the production of chlorosilanes (primarily: trichlorosilane) and the deposition of high purity poly-silicon from these chlorosilanes. The source for the chlorosilane production consists of eutectic or hypo-eutectic copper-silicon, the concentration range of said copper-silicon is between 10 and 16 wt% silicon. The eutectic or hypo-eutectic copper-silicon is cast in a shape suitable for a chlorination reactor, where it is exposed to a process gas, which consists, at least partially, of HCI. The gas reacts at the surface of the eutectic or hypo-eutectic copper-silicon and extracts silicon in the form of volatile chlorosilane. The depleted eutectic or hypo-eutectic material might be afterwards recycled in such a way that the amount of extracted silicon is replenished and the material is re-cast into the material shape desired.
摘要翻译：用于生产氯硅烷（主要是三氯硅烷）的方法和材料以及从这些氯硅烷沉积高纯度多晶硅。氯硅烷生产的来源由共晶或低共晶铜硅组成，所述铜 - 硅的浓度范围为10至16重量％的硅。共晶或低共晶铜 - 硅铸造成适合于氯化反应器的形状，其中它暴露于至少部分由HCl组成的工艺气体。气体在共晶或低共晶铜硅的表面反应，并以挥发性氯硅烷的形式提取硅。耗尽的共晶或低共晶材料可以随后再循环，使得提取的硅的量被补充并且材料被重铸成所需的材料形状。

2. 发明专利

CA2746752A1 METHOD AND APPARATUS FOR SILICON REFINEMENT 未知
公开(公告)号：CA2746752A1
公开(公告)日：2010-07-15
申请号：CA2746752
申请日：2009-12-23
申请人： ARISE TECHNOLOGIES CORP
发明人： BALKOS ATHANASIOS TOM , DAWKINS JEFFREY , DODD PETER
IPC分类号： C01B33/039 , C01B33/037
摘要： A method and respect material for the production of chlorosilanes (primarily: trichlorosilane) and the deposition of high purity poly-silicon from these chlorosilanes. The source for the chlorosilane production consists of eutectic or hypo-eutectic copper-silicon, the concentration range of said copper-silicon is between 10 and 16 wt% silicon. The eutectic or hypo-eutectic copper-silicon is cast in a shape suitable for a chlorination reactor, where it is exposed to a process gas, which consists, at least partially, of HCI. The gas reacts at the surface of the eutectic or hypo-eutectic copper-silicon and extracts silicon in the form of volatile chlorosilane. The depleted eutectic or hypo-eutectic material might be afterwards recycled in such a way that the amount of extracted silicon is replenished and the material is re-cast into the material shape desired.

3. 发明专利

AU5612799A Freeze protection apparatus for fluid transport passages 未知
公开(公告)号：AU5612799A
公开(公告)日：2000-04-03
申请号：AU5612799
申请日：1999-09-14
申请人： ARISE TECHNOLOGIES CORP
发明人： OBERHOLZER JOHANNES-ULRICH , ELZINGA DAVID , MACLELLAN IAN , MATHER DAVID W
IPC分类号： E03B7/10 , F24J2/46
摘要： The present invention provides a fluid handling apparatus for use in cold temperature conditions. In this respect, the apparatus of the present invention comprises a freeze protected conduit having a length comprising an elongated conduit for conveying or containing an aqueous liquid and an elongated compressible elastomeric material disposed within the conduit along its length. Alternatively, the conduit may comprise, at least in part, a substantially liquid impermeable membrane which is disposed in substantially adjacent relationship with a compressible elastomeric material. When exposed to freezing temperatures, aqueous liquid in conduits will freeze and expand. The compressible elastomeric material accommodates this expansion, thereby protecting the conduit from failure.

4. 发明专利

CA2746758A1 METHOD AND APPARATUS FOR THE PRODUCTION OF CHLOROSILANES 未知
公开(公告)号：CA2746758A1
公开(公告)日：2010-07-15
申请号：CA2746758
申请日：2009-12-23
申请人： ARISE TECHNOLOGIES CORP
发明人： BALKOS ATHANASIOS TOM , DAWKINS JEFFREY , DODD PETER
IPC分类号： C01B33/021 , B01J8/02 , C01B33/107
摘要： A method and respect material for the production of chlorosilanes (primarily: trichlorosilane) and the deposition of high purity poly-silicon from these chlorosilanes. The source for the chlorosilane production consists of eutectic or hypo-eutectic copper- silicon, the concentration range of said copper-silicon is between 10 and 16 wt% silicon. The eutectic or hypo-eutectic copper-silicon is cast in a shape suitable for a chlorination reactor, where it is exposed to a process gas, which consists, at least partially, of HCI. The gas reacts at the surface of the eutectic or hypo-eutectic copper-silicon and extracts silicon in the form of volatile chlorosilane. The depleted eutectic or hypo- eutectic material might be afterwards recycled in such a way that the amount of extracted silicon is replenished and the material is re-cast into the material shape desired.

5. 发明专利

CA2661047A1 LOW-TEMPERATURE DOPING PROCESSES FOR SILICON WAFER DEVICES 未知
公开(公告)号：CA2661047A1
公开(公告)日：2007-11-22
申请号：CA2661047
申请日：2007-05-15
申请人： ARISE TECHNOLOGIES CORP
发明人： SIVOTHTHAMAN SIVA , FARROKH-BAROUGHI MAHDI
IPC分类号： C30B25/20 , C30B25/02 , H01L31/042 , H01L31/18 , H01L49/02
摘要： A low temperature method and system configuration for depositing a doped silicon layer on a silicon substrate of a selected grade. The silicon substr ate for functioning as a light absorber and the doped silicon layer for func tioning as an emitter. The method comprises the acts of: positioning the sil icon substrate in a chamber suitable for chemical vapour deposition of the d oped silicon layer on the silicon substrate, an external surface of the sili con substrate suitable for promoting crystalline film growth; using a plural ity of process parameters for adjusting growth of the doped silicon layer, t he plurality of process parameters including a first process parameter of a process temperature for inhibiting diffusion of dopant atoms into the extern al surface of the silicon substrate, and a second process parameter of a hyd rogen dilution level for providing excess hydrogen atoms to affect a layer c rystallinity of the atomic structure of the doped silicon layer; exposing th e external surface of the silicon substrate in the chamber to a vapour at ap propriate ambient chemical vapour deposition conditions, the vapour includin g silicon atoms, dopant atoms and the excess hydrogen atoms, the atoms for u se in growing the doped silicon layer; and originating growth of the doped s ilicon layer on the external surface to form aninterface between the doped s ilicon layer and the silicon substrate, such that the doped silicon layer in cludes first atomic structural regions having a higher quality of the layer crystallinity next to the interface with adjacent second atomic structural r egions having a lower quality of the layer crystallinity with increasing con centrations of crystal defects for increasing thickness of the doped silicon layer from the interface. The resultant silicon substrate and doped layer ( or thin film) can be used in solar cell manufacturing.

6. 发明专利

CA2640278A1 SOLAR CELL 未知
公开(公告)号：CA2640278A1
公开(公告)日：2007-08-02
申请号：CA2640278
申请日：2007-01-10
申请人： ARISE TECHNOLOGIES CORP
发明人： ZUKOTYNSKI STEFAN , YEGHIKYAN DAVIT , RAYAPROL BHANU GANGADHAR , KHERANI NAZIR PYARALI
IPC分类号： H01L31/0376 , H01L31/0216 , H01L31/0224
摘要： The present invention provides a thin film amorphous silicon-crystalline silicon back heterojunction and back surface field device configuration for a heterojunction solar cell. The configuration is attained by the formation of heterojunctions on the back surface of crystalline silicon at low tempera tures. Low temperature fabrication allows for the application of low resolut ion lithography and/or shadow masking processes to produce the structures. T he shadowing losses are eliminated by positioning the electrical contacts at the back thereby removing them from the path of the incident light. Back co ntacts need optimization only for maximum charge carrier collection without bothering about shading losses. The open circuit voltage of the back heteroj unction device is higher than that of an all-crystalline device. The solar c ell configurations are equally amenable to crystalline silicon wafer absorbe r as well as thin silicon layers formed by using a variety of fabrication pr ocesses.

7. 发明公开

EP1979951A4 SOLAR CELL 有权
公开(公告)号：EP1979951A4
公开(公告)日：2010-08-04
申请号：EP07701665
申请日：2007-01-10
申请人： ARISE TECHNOLOGIES CORP
发明人： KHERANI NAZIR PYARALI , RAYAPROL BHANU GANGADHAR , YEGHIKYAN DAVIT , ZUKOTYNSKI STEFAN
IPC分类号： H01L31/0376 , H01L31/0216 , H01L31/0224
CPC分类号： H01L31/077 , H01L31/02167 , H01L31/022441 , H01L31/0745 , H01L31/0747 , Y02E10/50

8. 发明公开

EP2021533A4 LOW-TEMPERATURE DOPING PROCESSES FOR SILICON WAFER DEVICES 审中-公开
标题翻译：低温硅晶片掺杂的设备
公开(公告)号：EP2021533A4
公开(公告)日：2010-01-06
申请号：EP07719755
申请日：2007-05-15
申请人： ARISE TECHNOLOGIES CORP
发明人： SIVOTHTHAMAN SIVA , FARROKH-BAROUGHI MAHDI
IPC分类号： C30B25/20 , C30B25/02 , H01L31/042 , H01L31/18 , H01L49/02
CPC分类号： H01L31/1804 , C30B25/02 , C30B29/06 , H01L21/02381 , H01L21/02532 , H01L21/0257 , H01L21/0262 , H01L21/02634 , H01L31/072 , H01L31/0747 , Y02E10/547 , Y02P70/521

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