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1. 发明申请

US20180074934A1 METHOD FOR CHECKING EQUIVALENCE OF CODE, NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM, COMPUTER PROGRAM PRODUCT AND COMPUTER FOR IMPLEMENTING THE METHOD 审中-公开
公开(公告)号：US20180074934A1
公开(公告)日：2018-03-15
申请号：US15797446
申请日：2017-10-30
申请人： AREVA NP SAS
发明人： RICHARD KRECKEL , ANDREAS KUENZEL
IPC分类号： G06F11/36 , G06F9/45 , G06F9/44 , G05B9/02
CPC分类号： G06F11/36 , G05B9/02 , G06F8/427 , G06F8/433 , G06F8/71 , G21D3/04
摘要： A method checks the functional equivalence of two pieces of software for control systems, engineered from function block diagram with a plurality of interconnected function blocks. The method includes a) generating a first instance of compilable source code; b) parsing the first instance of source code; c) using the information from step b) to reconstruct a first data flow graph of the first instance of source code; d) generating a second instance of compilable source code from a second plurality of function block diagrams; e) parsing the second instance of source code; f) using the information from step e) to reconstruct a second data flow graph of the second instance of source code; g) comparing the first identified data flow graph and the second identified data flow graph, and checking if the transitive closure of input up to that node in the second instance of source code is the same.

2. 发明申请

US20170339803A1 VENTILATOR ARRANGEMENT, FAN FLAP CONFIGURATION AND RELATED CONTROL CABINET 审中-公开
公开(公告)号：US20170339803A1
公开(公告)日：2017-11-23
申请号：US15662590
申请日：2017-07-28
申请人： AREVA NP SAS
发明人： NORMAN KAUN
IPC分类号： H05K7/20
CPC分类号： H05K7/20572 , F04D25/166 , F04D27/003 , F04D27/005 , F24F7/007 , H05K7/20172 , H05K7/20181
摘要： A fan arrangement has a plurality of fans arranged in parallel to each other and configured to generate airflow along a common main flow direction. A flow channel is assigned to each fan, and a respective flow channel has a flap that can be swiveled between an open position and a closed position. The flap is constructed and positioned within the flow channel in such a way that it is supported by the airflow in the open position and brought into the closed position by a reverse flow opposing the airflow. This arrangement reliably prevents a fluidic short circuit in the event of failure of individual fans, and ensures natural draft convection in the event of failure of all fans. The flap is constructed in such a way that it is brought into the open position when no air is flowing due to its intrinsic weight.

3. 发明授权

US10547313B2 Circuit arrangement for a safety IandC system 有权
公开(公告)号：US10547313B2
公开(公告)日：2020-01-28
申请号：US15512765
申请日：2015-08-17
申请人： AREVA NP SAS
发明人： Guenther Auer , Johannes Weber
IPC分类号： H03K19/177 , G21D3/00
摘要： A circuit arrangement, in particular for a safety I&C system of a nuclear power plant, keeps a proven diagram-centric project-specific engineering approach known from CPU-based systems while reaping the benefits of FPGA technology. To this end, the circuit arrangement includes: a generic FPGA with a plurality of logic blocks, and at least one dedicated PLD which operates as an application-specific switch-matrix for the logic blocks.

4. 发明申请

US20170250690A1 CIRCUIT ARRANGEMENT FOR A SAFETY I&C SYSTEM 审中-公开
公开(公告)号：US20170250690A1
公开(公告)日：2017-08-31
申请号：US15512765
申请日：2015-08-17
申请人： AREVA NP SAS
发明人： GUENTHER AUER , JOHANNES WEBER
IPC分类号： H03K19/177 , G21D3/00
摘要： A circuit arrangement, in particular for a safety I&C system of a nuclear power plant, keeps a proven diagram-centric project-specific engineering approach known from CPU-based systems while reaping the benefits of FPGA technology. To this end, the circuit arrangement includes: a generic FPGA with a plurality of logic blocks, and at least one dedicated PLD which operates as an application-specific switch-matrix for the logic blocks.

5. 发明申请

WO2016079297A1 SEISMIC SENSOR UNIT AND ACCORDING EMERGENCY SHUTDOWN SYSTEM OF A NUCLEAR POWER PLANT 审中-公开
标题翻译：地震传感器单元和核电厂的紧急关闭系统
公开(公告)号：WO2016079297A1
公开(公告)日：2016-05-26
申请号：PCT/EP2015/077218
申请日：2015-11-20
申请人： AREVA NP SAS
发明人： WEBER, Johannes , EINZMANN, Klaus
IPC分类号： G01V1/18
CPC分类号： G01V1/184
摘要： The invention relates to a seismic sensor unit (4) for an emergency shutdown system (2) of a nuclear power plant, comprising - at least one accelerometer (6) for at least one axis, - a trigger module (8) which processes a signal derived from a measured signal of said accelerometer (6) and generates an output signal from which a trip signal is derived. It is an objective of the present invention to provide a reliable, robust, and non- complex seismic sensor unit (4) of such a type. The proposed solution according to the invention is characterized in that said trigger module (8) comprises an analog peak-hold-circuit (18) processing an input signal (X) and generating an output signal (Y) with the following properties: - if the input signal (X) is rising and the level of the output signal (Y) is below the level of the input signal (X), the output signal (Y) increases almost in- stantly with the input signal (X), - if the level of the input signal (X) is below the level of the output signal (Y), the output signal (Y) essentially keeps the current level unless a reset condition is reached.
摘要翻译：本发明涉及一种用于核电站的紧急停机系统（2）的地震传感器单元（4），包括：用于至少一个轴线的至少一个加速度计（6）; - 触发模块（8），其处理来自所述加速度计（6）的测量信号的信号，并且产生一个从中导出跳闸信号的输出信号。本发明的目的是提供一种这种类型的可靠，稳健且非复杂的地震传感器单元（4）。根据本发明的所提出的解决方案的特征在于，所述触发模块（8）包括处理输入信号（X）并产生具有以下特性的输出信号（Y）的模拟峰值保持电路（18）： - 如果输入信号（X）上升，输出信号（Y）的电平低于输入信号（X）的电平，输出信号（Y）的输入信号（X）几乎增加，如果输入信号（X）的电平低于输出信号（Y）的电平，则输出信号（Y）基本上保持当前电平，除非达到复位条件。

6. 发明申请

WO2016026823A1 CIRCUIT ARRANGEMENT FOR A SAFETY I&C SYSTEM 审中-公开
标题翻译：安全I＆C系统的电路安装
公开(公告)号：WO2016026823A1
公开(公告)日：2016-02-25
申请号：PCT/EP2015/068873
申请日：2015-08-17
申请人： AREVA NP SAS
发明人： AUER, Günther , WEBER, Johannes
IPC分类号： H03K19/177 , G21D3/00 , G11C7/00
CPC分类号： H03K19/17768 , G21D3/00 , H03K19/17728 , H03K19/17764 , Y02E30/39
摘要： A circuit arrangement, in particular for a safety I&C system (4) of a nuclear power plant (6), is to keep the proven diagram-centric project-specific engineering approach known from CPU-based systems while reaping the benefits of FPGA technology. To this end, the circuit arrangement according to the invention comprises: • a generic FPGA (18) with a number of logic blocks (20), and • at least one dedicated PLD (22) which operates as an application-specific switch-matrix for said logic blocks (20).
摘要翻译：特别是对于核电厂（6）的安全I＆C系统（4）的电路布置，是为了在获得FPGA技术的优势的同时，保持以CPU为基础的系统已知的以图为中心的项目特定工程方法。为此，根据本发明的电路装置包括：•具有多个逻辑块（20）的通用FPGA（18），以及至少一个专用的PLD（22），其作为应用特定的开关矩阵对于所述逻辑块（20）。

7. 发明申请

WO2016174132A1 METHOD FOR CHECKING EQUIVALENCE OF CODE 审中-公开
标题翻译：检查代码等同性的方法
公开(公告)号：WO2016174132A1
公开(公告)日：2016-11-03
申请号：PCT/EP2016/059479
申请日：2016-04-28
申请人： AREVA NP SAS
发明人： KRECKEL, Richard , KÜNZEL, Andreas
IPC分类号： G06F11/36 , G06F17/50
CPC分类号： G06F11/36 , G05B9/02 , G06F8/427 , G06F8/433 , G06F8/71 , G21D3/04
摘要： A method for checking the functional equivalence of two pieces of software for control systems, in particular control systems based on programmable logic controllers, engineered from function block diagrams (120, 196) with a plurality of interconnected function blocks, the method comprising the following steps: a) generating a first instance of compilable source code from a first plurality of function block diagrams (70, 74, 78) by virtue of a first code generator obeying to a first set of sequentialization rules; b) parsing said first instance of source code and identifying the set of all function block I/O ports and junction points (nodes) and the set of all connections between them (arcs) of the data flow; c) using the information from step b) to reconstruct a first data flow graph (86) of said first instance of source code in the upstream direction; d) generating a second instance of compilable source code from a second plurality of function block diagrams (90, 94, 98) by virtue of the same or a second code generator obeying a second set of sequentialization rules; e) parsing said second instance of source code and identifying the set of all function block I/O ports and junction points (nodes) and the set of all connections between them (arcs) of the data flow; f) using the information from step e) to reconstruct a second data flow graph (106) of said second instance of source code in the upstream direction; g) comparing said first identified data flow graph (86) and said second identified data flow graph (106) with each other, node by node, and thereby checking if the transitive closure of input up to that node in said second instance of source code is the same as in said first instance of source code.
摘要翻译：一种用于检查用于控制系统的两个软件的功能等同的方法，特别是基于可编程逻辑控制器的控制系统，其由具有多个互连的功能块的功能框图（120,196）设计，所述方法包括以下步骤：a）凭借符合第一组顺序规则的第一代码生成器，从第一多个功能块图（70,74,78）生成可编译源代码的第一实例; b）解析所述源代码的第一实例并且识别所述数据流的所有功能块I / O端口和连接点（节点）以及它们之间的所有连接的集合的集合; c）使用来自步骤b）的信息来重建所述上游方向上的所述第一源代码实例的第一数据流图（86）; d）借助于遵循第二组顺序规则的相同或第二代码生成器，从第二多个功能块图（90,94,98）生成可编译源代码的第二实例; e）解析所述源代码的第二实例并且识别所述数据流的所有功能块I / O端口和连接点（节点）和它们之间的所有连接的集合的集合; f）使用来自步骤e）的信息来重构所述上游方向上所述源代码第二实例的第二数据流图（106）; g）逐节点将所述第一识别数据流图（86）和所述第二识别数据流图（106）进行比较，从而检查所述第二个源代码中直到该节点的输入的传递闭包与源代码的第一个实例相同。

8. 发明公开

EP3089037A1 METHOD FOR CHECKING EQUIVALENCE OF CODE 有权转让
标题翻译： VERFAHREN ZURÜBERPRÜFUNGDERÄQUIVALENZVON代码
公开(公告)号：EP3089037A1
公开(公告)日：2016-11-02
申请号：EP15165729.3
申请日：2015-04-29
申请人： Areva NP SAS
发明人： KRECKEL, Richard , KÜNZEL, Andreas
IPC分类号： G06F11/36 , G06F17/50
CPC分类号： G06F11/36 , G05B9/02 , G06F8/427 , G06F8/433 , G06F8/71 , G21D3/04
摘要： A method for checking the functional equivalence of two pieces of software for control systems, in particular control systems based on programmable logic controllers, engineered from function block diagrams (120, 196) with a plurality of interconnected function blocks, the method comprising the following steps:
a) generating a first instance of compilable source code from a first plurality of function block diagrams (70, 74, 78) by virtue of a first code generator obeying to a first set of sequentialization rules;
b) parsing said first instance of source code and identifying the set of all function block I/O ports and junction points (nodes) and the set of all connections between them (arcs) of the data flow;
c) using the information from step b) to reconstruct a first data flow graph (86) of said first instance of source code in the upstream direction;
d) generating a second instance of compilable source code from a second plurality of function block diagrams (90, 94, 98) by virtue of the same or a second code generator obeying a second set of sequentialization rules;
e) parsing said second instance of source code and identifying the set of all function block I/O ports and junction points (nodes) and the set of all connections between them (arcs) of the data flow;
f) using the information from step e) to reconstruct a second data flow graph (106) of said second instance of source code in the upstream direction;
g) comparing said first identified data flow graph (86) and said second identified data flow graph (106) with each other, node by node, and thereby checking if the transitive closure of input up to that node in said second instance of source code is the same as in said first instance of source code.
摘要翻译：一种用于检查用于控制系统的两个软件的功能等同的方法，特别是基于可编程逻辑控制器的控制系统，其由具有多个互连功能块的功能框图（120,196）设计，所述方法包括以下步骤：a）凭借符合第一组顺序化规则的第一代码生成器，从第一多个功能块图（70,74,78）生成可编译源代码的第一实例; b）解析所述源代码的第一实例并且识别所述数据流的所有功能块I / O端口和连接点（节点）和它们之间的所有连接的集合的集合; c）使用来自步骤b）的信息来重构所述上游方向上的所述第一源代码实例的第一数据流图（86）; d）借助于遵循第二组顺序规则的相同或第二代码生成器从第二多个功能块图（90,94,98）生成可编译源代码的第二实例; e）解析所述源代码的第二实例并且识别所述数据流的所有功能块I / O端口和连接点（节点）的集合以及它们之间的所有连接的集合（arcs）; f）使用来自步骤e）的信息来重构所述上游方向上所述源代码的第二实例的第二数据流图（106）; g）逐节点将所述第一识别数据流图（86）和所述第二识别数据流图（106）进行比较，从而检查所述第二个源代码中直到该节点的输入的传递闭包与源代码的第一个实例相同。

9. 发明公开

EP3023814A1 Seismic sensor unit and according emergency shutdown system of a nuclear power plant 审中-公开
标题翻译：地震活动
公开(公告)号：EP3023814A1
公开(公告)日：2016-05-25
申请号：EP14194340.7
申请日：2014-11-21
申请人： Areva NP SAS
发明人： WEBER, Johannes , Einzmann, Klaus
IPC分类号： G01V1/18
CPC分类号： G01V1/184
摘要： The invention relates to a seismic sensor unit (4) for an emergency shutdown system (2) of a nuclear power plant, comprising
• at least one accelerometer (6) for at least one axis,
• a trigger module (8) which processes a signal derived from a measured signal of said accelerometer (6) and generates an output signal from which a trip signal is derived.
It is an objective of the present invention to provide a reliable, robust, and non-complex seismic sensor unit (4) of such a type. The proposed solution according to the invention is characterized in that said trigger module (8) comprises an analog peak-hold-circuit (18) processing an input signal (X) and generating an output signal (Y) with the following properties:
• if the input signal (X) is rising and the level of the output signal (Y) is below the level of the input signal (X), the output signal (Y) increases almost instantly with the input signal (X),
• if the level of the input signal (X) is below the level of the output signal (Y), the output signal (Y) essentially keeps the current level unless a reset condition is reached.
摘要翻译：本发明涉及一种用于核电站的紧急停机系统（2）的地震传感器单元（4），包括至少一个用于至少一个轴的加速度计（6），触发模块（8），其中，处理从所述加速度计（6）的测量信号导出的信号，并产生从其导出跳闸信号的输出信号。本发明的目的是提供一种这种类型的可靠，稳健且非复杂的地震传感器单元（4）。根据本发明的所提出的解决方案的特征在于，所述触发模块（8）包括处理输入信号（X）并产生具有以下特性的输出信号（Y）的模拟峰值保持电路（18）：¢ 如果输入信号（X）上升并且输出信号（Y）的电平低于输入信号（X）的电平，则输入信号（Y）随输入信号（X）几乎立即增加，¢ 如果输入信号（X）的电平低于输出信号（Y）的电平，则输出信号（Y）基本上保持当前电平，除非达到复位条件。

10. 发明公开

EP2988420A1 Circuit Arrangement for a Safety I&C System 有权转让
标题翻译： Schaltungsanordnungfürein Sicherheits-I＆C-System
公开(公告)号：EP2988420A1
公开(公告)日：2016-02-24
申请号：EP14181534.0
申请日：2014-08-20
申请人： Areva NP SAS
发明人： Auer, Günther , Weber, Johannes
IPC分类号： H03K19/177 , G21D3/00 , G11C7/00
CPC分类号： H03K19/17768 , G21D3/00 , H03K19/17728 , H03K19/17764 , Y02E30/39
摘要： A circuit arrangement, in particular for a safety I&C system (4) of a nuclear power plant (6), is to keep the proven diagram-centric project-specific engineering approach known from CPU-based systems while reaping the benefits of FPGA technology. To this end, the circuit arrangement according to the invention comprises
• a generic FPGA (18) with a number of logic blocks (20), and
• at least one dedicated PLD (22) which operates as an application-specific switch-matrix for said logic blocks (20).
摘要翻译：特别是对于核电站（6）的安全I＆C系统（4）的电路布置，是为了在获得FPGA技术的优势的同时，保持以CPU为基础的系统已知的以图表为中心的项目特定工程方法。为此，根据本发明的电路装置包括具有多个逻辑块（20）的通用FPGA（18），以及至少一个专用PLD（22），其作为特定于应用的开关 - 矩阵，用于所述逻辑块（20）。

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