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1. 发明申请

WO2009042490A3 IMPROVED NITROGEN PROFILE IN HIGH-K DIELECTRICS USING ULTRATHIN DISPOSABLE CAPPING LAYERS 审中-公开
公开(公告)号：WO2009042490A3
公开(公告)日：2009-04-02
申请号：PCT/US2008/076824
申请日：2008-09-18
申请人： TEXAS INSTRUMENTS INCORPORATED , ALSHAREEF, Husam , LOPEZ, Manuel, Quevedo
发明人： ALSHAREEF, Husam , LOPEZ, Manuel, Quevedo
IPC分类号： H01L21/336
摘要： Metal Oxide Semiconductor (MOS) transistors fabricated using current art may utilize a nitridation process on the gate dielectric (100) to improve transistor reliability. Nitridation by the current art, which involves exposing the gate dielectric to a nitridation source, produces a significant concentration of nitrogen at the interface of the gate dielectric and the transistor substrate (102), which adversely affects transistor performance. This invention comprises the process of depositing a sacrificial layer (104) on the gate dielectric prior to nitridation (106), exposing the sacrificial layer to a nitridation source, during which time nitrogen atoms diffuse through the sacrificial layer into the gate dielectric, then removing the sacrificial layer without degrading the gate dielectric. Work associated with this invention on high-k gate dielectrics has demonstrated a 20 percent reduction in nitrogen concentration at the gate dielectric - transistor substrate interface.

2. 发明申请

WO2008121939A1 PLASMA NITRIDED GATE OXIDE, HIGH-K METAL GATE BASED CMOS DEVICE 审中-公开
标题翻译：等离子体氮化物氧化物，高K金属栅基CMOS器件
公开(公告)号：WO2008121939A1
公开(公告)日：2008-10-09
申请号：PCT/US2008/058857
申请日：2008-03-31
申请人： TEXAS INSTRUMENTS INCORPORATED , ALSHAREEF, Husam, Niman , QUEVEDO-LOPEZ, Manuel
发明人： ALSHAREEF, Husam, Niman , QUEVEDO-LOPEZ, Manuel
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/02164 , H01L21/02181 , H01L21/02189 , H01L21/02332 , H01L21/0234 , H01L21/28194 , H01L21/28202 , H01L21/3145 , H01L21/31604 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/823828 , H01L27/092 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518
摘要： In accordance with the invention, there are CMOS devices (100) and semiconductor devices and methods of fabricating them. The CMOS device can include a substrate (110) including a first active region (112) and a second active region (114) and a first transistor device over the first active region, wherein the first transistor device includes a high-K layer (120) over the first active region, a first dielectric capping layer on the high-K layer, and a first metal gate layer over the first dielectric capping layer (132). The CMOS device can also include a second transistor device over the second active region, wherein the second transistor device includes a high-K layer over the second active region, a second dielectric capping layer (134) on the second high-K layer, and a second metal gate layer over the second dielectric capping layer.
摘要翻译：根据本发明，存在CMOS器件（100）和半导体器件及其制造方法。 CMOS器件可以包括在第一有源区上包括第一有源区（112）和第二有源区（114）和第一晶体管器件的衬底（110），其中第一晶体管器件包括高K层（120 ），在高K层上的第一介电覆盖层和在第一介电覆盖层（132）上的第一金属栅极层。 CMOS器件还可以包括在第二有源区上的第二晶体管器件，其中第二晶体管器件包括第二有源区上的高K层，第二高K层上的第二介电覆盖层（134），以及在第二介电覆盖层上方的第二金属栅极层。

3. 发明申请

WO2014158970A1 FRACTIONAL ORDER CAPACITOR BASED ON DIELECTRIC POLYMER DOPED WITH CONDUCTIVE NANO-FILLERS 审中-公开
标题翻译：基于导电纳米填料的介电聚合物的分层订购电容器
公开(公告)号：WO2014158970A1
公开(公告)日：2014-10-02
申请号：PCT/US2014/021173
申请日：2014-03-06
申请人： SAUDI BASIC INDUSTRIES CORPORATION , ALMADHOUN, Mahmoud, N. , ELSHURAFA, Amro , SALAMA, Khaled , ALSHAREEF, Husam, N.
发明人： ALMADHOUN, Mahmoud, N. , ELSHURAFA, Amro , SALAMA, Khaled , ALSHAREEF, Husam, N.
IPC分类号： H01G4/20
CPC分类号： H01G4/005 , B82Y30/00 , H01G4/206 , H03K5/14 , H05K1/182
摘要： The invention discloses a fractional order capacitor. The fractional order capacitor is defined as having an adapted dielectric impedance. To obtain the required impedance of the dielectric layer, conductive nanofillers are added to the dielectric, therefore resulting in the formation of a dielectric nanocomposite layer. In the invention a polymer matrix (like PVDF-TRFE) is combine with graphene. The graphene can be partially or completely unoxidized. The invention discloses a fractional order capacitor comprising a dielectric nanocomposite layer of thickness t, comprising a first side and a second side opposite the first side, a first electrode layer coupled to the first side of the dielectric nanocomposite layer, a second electrode layer coupled to the second side of the dielectric layer, a complex impedamce phase angle dependent on at least a material weight percentage of filler material in a dielectric nanocomposite layer.
摘要翻译：本发明公开了一种分数阶电容器。分数阶电容器被定义为具有适应的介电阻抗。为了获得电介质层的所需阻抗，将导电纳米填料添加到电介质中，从而形成电介质纳米复合层。在本发明中，聚合物基质（如PVDF-TRFE）与石墨烯结合。石墨烯可以部分或完全未氧化。本发明公开了一种包括厚度t的电介质纳米复合层的分数阶电容器，包括第一侧和与第一侧相对的第二侧，耦合到电介质纳米复合层的第一侧的第一电极层，耦合到电介质层的第二面，复阻抗相位角取决于电介质纳米复合材料层中填料材料的至少材料重量百分比。

4. 发明申请

WO2014058860A1 GRAPHENE-BASED COMPOSITE MATERIALS, METHOD OF MANUFACTURE AND APPLICATIONS THEREOF 审中-公开
标题翻译：基于石墨的复合材料，其制造方法及其应用
公开(公告)号：WO2014058860A1
公开(公告)日：2014-04-17
申请号：PCT/US2013/063850
申请日：2013-10-08
申请人： SAUDI BASIC INDUSTRIES CORPORATION , ALSHAREEF, Husam N.
发明人： ALSHAREEF, Husam N. , ALMADHOUN, Mahmoud , BHANSALI, Unnat S. , XAVIER, Prince
IPC分类号： C08K3/04 , C08K9/02 , C08L27/12
CPC分类号： H01G4/14 , C08K3/04 , C08K9/02 , C08L2203/20 , C08L2666/55 , Y10S977/779 , C08L101/00
摘要： Disclosed herein is a composite material comprising a relaxor ferroelectric material and a hydrazine-reduced graphene oxide, wherein the weight ratio of the composite material to the hydrazine-reduced graphene oxide is 9:1 to 200:1. The composite materials have high dielectric permittivity and low dielectric losses and can be used to manufacture various high dielectric permittivity components.
摘要翻译：本发明公开了一种复合材料，其包含一种弛豫铁电材料和一种还原型的氧化亚锡，其中复合材料与肼还原型石墨烯氧化物的重量比为9:1至200:1。复合材料具有高介电常数和低介电损耗，可用于制造各种高介电常数成分。

5. 发明申请

WO2016028356A1 NON-VOLATILE FERROELECTRIC MEMORY CELLS WITH MULTILEVEL OPERATION 审中-公开
标题翻译：具有多次操作的非挥发性电磁记忆体
公开(公告)号：WO2016028356A1
公开(公告)日：2016-02-25
申请号：PCT/US2015/033983
申请日：2015-06-03
申请人： SABIC GLOBAL TECHOLOGIES B.V , PARK, Ji, Hoon , ALSHAREEF, Husam, N. , KHAN, Mohd, A. , ODEN, Ihab, N.
发明人： PARK, Ji, Hoon , ALSHAREEF, Husam, N. , KHAN, Mohd, A. , ODEN, Ihab, N.
IPC分类号： H01L43/08 , G11C11/15
CPC分类号： G11C11/2275 , G11C11/221 , G11C11/2273 , G11C11/2277 , G11C11/5657 , H01L27/11509 , H01L27/20
摘要： Ferroelectric components, such as the ferroelectric field effect transistors (FeFETs), ferroelectric capacitors and ferroelectric diodes described above may be operated as multi-level memory cells as described by the present invention. Storing multiple bits of information in each multi-level memory cell may be performed by a controller coupled to an array of the ferroelectric components configured as ferroelectric memory cells. The controller may execute the steps of receiving a bit pattern for writing to a multi-level memory cell comprising a ferroelectric layer; selecting a pulse duration for applying a write pulse to the memory cell based, at least in part, on the received bit pattern; and applying at least one write pulse to the memory cell having the selected pulse duration, in which the at least one write pulse creates a remnant polarization within the ferroelectric layer that is representative of the received bit pattern.
摘要翻译：诸如铁电场效应晶体管（FeFET），铁电电容器和铁电二极管的铁电元件可以作为如本发明所述的多电平存储器单元来操作。在每个多级存储器单元中存储多个位的信息可以由耦合到被配置为铁电存储单元的铁电元件阵列的控制器来执行。控制器可以执行以下步骤：接收用于写入到包括铁电层的多层存储单元的位模式; 至少部分地基于所接收的位模式，选择用于将写入脉冲施加到存储器单元的脉冲持续时间; 以及向具有所选择的脉冲持续时间的存储单元施加至少一个写入脉冲，其中所述至少一个写入脉冲在所述铁电层内产生代表所接收的位模式的剩余极化。

6. 发明申请

WO2013184797A1 FERROELECTRIC DEVICES, INTERCONNECTS, AND METHODS OF MANUFACTURE THEREOF 审中-公开
标题翻译：电磁装置，互连及其制造方法
公开(公告)号：WO2013184797A1
公开(公告)日：2013-12-12
申请号：PCT/US2013/044308
申请日：2013-06-05
申请人： SAUDI BASIC INDUSTRIES CORPORATION , ALSHAREEF, Husam N.
发明人： ALSHAREEF, Husam N. , UNNAT, Bhansali , KHAN, Mohd Adnan , SALEH, Moussa M. , ODEH, Ihab N.
IPC分类号： H01L49/02 , C08G61/12 , C08L25/18 , H01B1/12 , H01G4/008 , H01G4/14 , H01L23/532 , H01L51/00 , G11C11/22 , H01L27/10
CPC分类号： H01L51/102 , B82Y10/00 , C08G61/126 , C08G2261/1424 , C08G2261/3223 , C08G2261/51 , C08G2261/794 , C08G2261/92 , C08G2261/95 , C08L25/18 , C08L65/00 , G11C11/221 , H01B1/127 , H01B1/128 , H01G4/18 , H01G4/206 , H01G7/06 , H01L27/101 , H01L28/55 , H01L28/60 , H01L51/0001 , H01L51/0037 , H01L51/0591
摘要： A doped electroconductive organic polymer is used for forming the electrode of a ferroelectric device or an interconnect. An exemplary ferroelectric device is a ferrelectric capacitor comprising: a substrate (101); a first electrode (106) disposed on the substrate; a ferroelectric layer (112) disposed on and in contact with the first electrode; and a second electrode (116) disposed on and in contact with the ferroelectric layer, wherein at least one of the first electrode and the second electrode is an organic electrode comprising a doped electroconductive organic polymer, for example DMSO-doped PEDOT-PSS.
摘要翻译：掺杂的导电有机聚合物用于形成铁电体器件或互连件的电极。示例性的铁电体装置是一种电介质电容器，包括：基板（101）; 设置在所述基板上的第一电极（106）设置在第一电极上并与第一电极接触的铁电层（112）; 以及设置在铁电层上并与铁电层接触的第二电极（116），其中第一电极和第二电极中的至少一个是包括掺杂的导电有机聚合物（例如DMSO掺杂的PEDOT-PSS）的有机电极。

7. 发明申请

WO2014158956A1 FERROELECTRIC CAPACITOR WITH IMPROVED FATIGUE AND BREAKDOWN PROPERTIES 审中-公开
标题翻译：具有改进的疲劳和断裂特性的电磁电容器
公开(公告)号：WO2014158956A1
公开(公告)日：2014-10-02
申请号：PCT/US2014/021091
申请日：2014-03-06
申请人： SAUDI BASIC INDUSTRIES CORPORATION , KHAN, Mohd, A. , ALSHAREEF, Husam, N. , ODEH, Ihab, N. , ALMADHOUN, Mahmoud, N.
发明人： KHAN, Mohd, A. , ALSHAREEF, Husam, N. , ODEH, Ihab, N. , ALMADHOUN, Mahmoud, N.
IPC分类号： H01L51/05 , G11C13/02 , H01L49/02 , G11C11/22
CPC分类号： G11C11/22 , G11C11/221 , H01L28/55 , H01L51/004 , H01L51/0043 , H01L51/0591 , Y10T428/24802
摘要： Disclosed is a ferroelectric material (12) and methods for its use in capacitors. The ferroelectric material (12) comprises a polymer blend comprising a ferroelectric polymer (12a) and a dielectric polymer (12b) having a low dielectric constant. The dielectric polymer (12b) can phase separate from the ferroelectric polymer (12a) such that a plurality of separated regions (12b) are formed within the ferroelectric polymer (12a). The ferroelectric material (12) is disposed between two electrodes (11) and (13). The plurality of regions (12b) act as charge-trap regions to store charge and prevent charge carriers to move freely throughout the ferroelectric polymer (12a).
摘要翻译：公开了铁电材料（12）及其用于电容器的方法。铁电材料（12）包括包含铁电聚合物（12a）和具有低介电常数的电介质聚合物（12b）的聚合物共混物。电介质聚合物（12b）可以与铁电聚合物（12a）相分离，使得在铁电聚合物（12a）内形成多个分离区域（12b）。铁电材料（12）设置在两个电极（11）和（13）之间。多个区域（12b）充当电荷捕获区域以存储电荷并防止电荷载流子在整个铁电聚合物（12a）中自由移动。

8. 发明申请

WO2014058858A1 RESISTIVE MEMORY DEVICE FABRICATED FROM SINGLE POLYMER MATERIAL 审中-公开
标题翻译：由单一聚合物材料制成的电阻式存储器件
公开(公告)号：WO2014058858A1
公开(公告)日：2014-04-17
申请号：PCT/US2013/063847
申请日：2013-10-08
申请人： SAUDI BASIC INDUSTRIES CORPORATION , ALSHAREEF, Husam N.
发明人： ALSHAREEF, Husam N. , KHAN, Mohd Adnan , BHANSALI, Unnat S. , ALMADHOUN, Mahmoud
IPC分类号： G11C11/34 , G11C13/00 , H01L27/28 , H01L27/24 , H01L45/00 , H01L51/05 , H01L51/00
CPC分类号： H01L45/1253 , G11C13/0016 , G11C2213/15 , H01L27/281 , H01L45/16 , H01L51/0037 , H01L51/0575 , H01L51/0591 , H01L51/102
摘要： A polymer-based device comprising a substrate; a first electrode disposed on the substrate; an active polymer layer disposed on and in contact with the first electrode; and a second electrode disposed on and in contact with the active polymer layer, wherein the first and the second electrodes are organic electrodes comprising a doped electroconductive organic polymer, the active polymer layer comprises the electroconductive organic polymer of the first and the second electrodes, and the first and the second electrodes have conductivity at least three orders of magnitude higher than the conductivity of the active polymer layer.
摘要翻译：一种基于聚合物的装置，包括基底; 设置在所述基板上的第一电极; 设置在第一电极上并与第一电极接触的活性聚合物层; 以及设置在所述活性聚合物层上并与所述活性聚合物层接触的第二电极，其中所述第一和第二电极是包含掺杂的导电有机聚合物的有机电极，所述活性聚合物层包含所述第一和第二电极的导电有机聚合物，以及第一和第二电极具有比活性聚合物层的电导率高至少三个数量级的导电性。

9. 发明申请

WO2009042490A2 IMPROVED NITROGEN PROFILE IN HIGH-K DIELECTRICS USING ULTRATHIN DISPOSABLE CAPPING LAYERS 审中-公开
标题翻译：使用ULTRATHIN一次性覆盖层改进高K介质中氮的性能
公开(公告)号：WO2009042490A2
公开(公告)日：2009-04-02
申请号：PCT/US2008076824
申请日：2008-09-18
申请人： TEXAS INSTRUMENTS INC , ALSHAREEF HUSAM , LOPEZ MANUEL QUEVEDO
发明人： ALSHAREEF HUSAM , LOPEZ MANUEL QUEVEDO
IPC分类号： H01L21/336
CPC分类号： H01L21/28238 , H01L21/28202 , H01L21/823857 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： Metal Oxide Semiconductor (MOS) transistors fabricated using current art may utilize a nitridation process on the gate dielectric (100) to improve transistor reliability. Nitridation by the current art, which involves exposing the gate dielectric to a nitridation source, produces a significant concentration of nitrogen at the interface of the gate dielectric and the transistor substrate (102), which adversely affects transistor performance. This invention comprises the process of depositing a sacrificial layer (104) on the gate dielectric prior to nitridation (106), exposing the sacrificial layer to a nitridation source, during which time nitrogen atoms diffuse through the sacrificial layer into the gate dielectric, then removing the sacrificial layer without degrading the gate dielectric. Work associated with this invention on high-k gate dielectrics has demonstrated a 20 percent reduction in nitrogen concentration at the gate dielectric - transistor substrate interface.
摘要翻译：使用现有技术制造的金属氧化物半导体（MOS）晶体管可以在栅极电介质（100）上利用氮化工艺来提高晶体管的可靠性。现有技术的氮化（其涉及将栅极电介质暴露于氮化源）会在栅极电介质和晶体管衬底（102）的界面处产生显着的氮浓度，这会不利地影响晶体管性能。本发明包括在氮化（106）之前在栅极电介质上沉积牺牲层（104），暴露牺牲层到氮化源的过程，在此期间氮原子通过牺牲层扩散到栅极电介质中，然后去除牺牲层而不降低栅极电介质。与本发明有关的用于高k栅极电介质的工作已经证明在栅极电介质 - 晶体管基底界面处的氮浓度降低了20％。

10. 发明申请

WO2007025277A3 METHODS FOR DUAL METAL GATE COMPLEMENTARY METAL OXIDE SEMICONDUCTOR INTEGRATION 审中-公开
标题翻译：双金属互补金属氧化物半导体集成方法
公开(公告)号：WO2007025277A3
公开(公告)日：2007-08-02
申请号：PCT/US2006033637
申请日：2006-08-25
申请人： SEMATECH INC , SONG SEUNG-CHUL , ZHANG ZHIBO , LEE BYOUNG HUN , MOUMEN NAIM , BARNETT JOEL , HUSSAIN MUHAMMAD MUSTAFA , CHOI RINO , ALSHAREEF HUSAM
发明人： SONG SEUNG-CHUL , ZHANG ZHIBO , LEE BYOUNG HUN , MOUMEN NAIM , BARNETT JOEL , HUSSAIN MUHAMMAD MUSTAFA , CHOI RINO , ALSHAREEF HUSAM
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： Methods for fabricating two metal gate stacks for complementary metal oxide semiconductor (CMOS) devices are provided. A first metal layer may be deposited onto a gate dielectric. Next a mask layer may be deposited on the first metal layer and subsequently etch. The first metal layer is then etched. Without removing the mask layer, a second metal layer may be deposited. In one embodiment, the mask layer is a second metal layer. In other embodiments, the mask layer is a silicon layer. Subsequent fabrication steps include depositing another metal layer (e.g., another PMOS metal layer), depositing a cap, etching the cap to define gate stacks, and simultaneously etching the first and second gate region having a similar thickness with differing metal layers.
摘要翻译：提供了用于制造用于互补金属氧化物半导体（CMOS）器件的两个金属栅极叠层的方法。可以将第一金属层沉积到栅极电介质上。接下来，掩模层可以沉积在第一金属层上并随后蚀刻。然后蚀刻第一金属层。在不去除掩模层的情况下，可沉积第二金属层。在一个实施例中，掩模层是第二金属层。在其他实施例中，掩模层是硅层。随后的制造步骤包括沉积另一金属层（例如，另一个PMOS金属层），沉积帽，蚀刻帽以限定栅极堆叠，以及同时用不同的金属层蚀刻具有相似厚度的第一和第二栅极区域。

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