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1. 发明专利

JP3532834B2 High frequency amplifier bias circuit, high-frequency power amplifier and a communication device 有权
公开(公告)号：JP3532834B2
公开(公告)日：2004-05-31
申请号：JP2000192836
申请日：2000-06-27
申请人：富士通カンタムデバイス株式会社
发明人：直行宮沢
IPC分类号： H03F1/02 , H03F1/30 , H03F1/52 , H03F3/19 , H03F3/24 , H04B1/04
CPC分类号： H03F1/302 , H03F2200/294

2. 发明专利

JP2004102160A Light modulator and its manufacturing method 有权
公开(公告)号：JP2004102160A
公开(公告)日：2004-04-02
申请号：JP2002267090
申请日：2002-09-12
申请人： Fujitsu Ltd , Fujitsu Quantum Devices Ltd , 富士通カンタムデバイス株式会社 , 富士通株式会社
发明人： OTAKE FUMIO , SODA HARUHISA
IPC分类号： G02F1/025 , G02B6/12 , G02F1/015 , G02F1/225
CPC分类号： G02F1/2257 , G02B2006/12142
摘要： PROBLEM TO BE SOLVED: To provide a light modulator in which a modulation voltage is reduced, and to provide a method for manufacturing the light modulator having such an effect. SOLUTION: The light modulator is provided with upper clad layers 9a, 9b which are disposed on the upper part of optical waveguides 2a, 2b and are P-type or N-type and a plurality of modulation electrodes 4a, 4b which are disposed separately from each other on the upper clad layers 9a, 9b in the extended part of the optical waveguides 2a, 2b and applies a modulation signal to the optical waveguides 2a, 2b. The upper clad layers 9a, 9b have first regions located just under the plurality of modulation electrodes 4a, 4b and a second region located between the first regions. On the second region, separation parts 6a, 6b which electrically separate the first regions are disposed. The separation parts 6a, 6b are made of, for example, a semiconductor layer having a high resistance, a semiconductor layer of the conductivity type opposite to the conductivity type of the first region and the like. Further, the light modulator is preferably constituted in such a manner that the second region is depleted. COPYRIGHT: (C)2004,JPO

3. 发明专利

JP2004095637A Semiconductor device and method for manufacturing the same 有权
公开(公告)号：JP2004095637A
公开(公告)日：2004-03-25
申请号：JP2002251266
申请日：2002-08-29
申请人： Fujitsu Ltd , Fujitsu Quantum Devices Ltd , 富士通カンタムデバイス株式会社 , 富士通株式会社
发明人： MAKIYAMA KOZO , TAKAHASHI TAKESHI , NISHI SHINKO
IPC分类号： H01L21/28 , H01L21/285 , H01L21/335 , H01L21/338 , H01L29/41 , H01L29/417 , H01L29/423 , H01L29/812
CPC分类号： H01L29/66462 , H01L21/28587 , H01L29/42316
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which has a mushroom gate covered with an interlayer insulating film and is suppressed in increase in parasitic capacitance, and to provide a manufacturing method therefor.
SOLUTION: The method for manufacturing the semiconductor device includes a process (a) of forming the mushroom gate which has a fine gate and an over gate on a substrate across an active region, a process (b) of coating the substrate with a 1st organic material film to cover the mushroom gate, a process (c) of patterning the 1st organic material film to leave it only nearby the mushroom gate, a process (d) of coating the substrate with a 2nd organic material film which has a different chemical property to cover the residual 1st organic material film, a process (e) of forming an opening on the 2nd organic material film to expose the 1st organic material film, and a process (f) of dissolving and removing the 1st organic material film in the opening to form a cavity in the 2nd organic material film.
COPYRIGHT: (C)2004,JPO

4. 发明专利

JP3504598B2 Balanced frequency multiplier for microwave or millimeter wave 有权
公开(公告)号：JP3504598B2
公开(公告)日：2004-03-08
申请号：JP2000248782
申请日：2000-08-18
申请人：富士通カンタムデバイス株式会社
发明人：秀幸内野
IPC分类号： H03B19/14 , H03B19/18
CPC分类号： H03B19/14

5. 发明专利

JP3501284B2 A method of manufacturing a semiconductor device 有权
公开(公告)号：JP3501284B2
公开(公告)日：2004-03-02
申请号：JP2001101443
申请日：2001-03-30
申请人：富士通カンタムデバイス株式会社
发明人：浩遠藤
IPC分类号： H01L29/41 , H01L21/331 , H01L21/338 , H01L29/737 , H01L29/812
CPC分类号： H01L29/66878 , H01L29/66318 , H01L29/7371

6. 发明专利

JP2003298165A Optical semiconductor device and its manufacturing method 有权
标题翻译：光学半导体器件及其制造方法
公开(公告)号：JP2003298165A
公开(公告)日：2003-10-17
申请号：JP2002098035
申请日：2002-03-29
申请人： Fujitsu Quantum Devices Ltd , 富士通カンタムデバイス株式会社
发明人： OSAKA SHIGEO
IPC分类号： H01L21/318 , H01L33/44 , H01S5/02 , H01S5/028
CPC分类号： H01S5/028 , H01L33/44 , H01S5/0282
摘要： PROBLEM TO BE SOLVED: To effectively prevent a laminated body of an optical semiconductor device from being spoiled by components of a protection film, thus improving a COD.
SOLUTION: The optical semiconductor device has the laminated body constituting the optical semiconductor device, an intermediate film provided on an optical entrance or exit plane of the laminated body, and the protection film provided by an ion assist evaporation on the intermediate film. The optical semiconductor device is characterized in that a larger amount of ions irradiation is applied on the protection film than on the intermediate film. Since the intermediate film is formed by the relatively low amount of ions irradiation, it is possible to restrict a state that the optical entrance or exit plane is spoiled by an ions collision. Further, a method for manufacturing the device has a first step of forming the intermediate film on the optical entrance or exit plane of the laminated body constituting the optical semiconductor device at a first growing rate by use of an ion assist evaporating method, and a second step of forming the protection film on the intermediate film at a lower growing rate than the first growing rate by use of the ion assist evaporating method.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：为了有效地防止光学半导体器件的层叠体被保护膜的部件损坏，从而提高了COD。解决方案：光学半导体器件具有构成光学半导体器件的层叠体，设置在层叠体的光学入射面或出射面上的中间膜，以及通过中间膜上的离子辅助蒸发提供的保护膜。光学半导体器件的特征在于，在保护膜上施加比在中间膜上更大量的离子照射。由于通过相对较少的离子照射形成中间膜，因此可以限制光入射面或离开平面被离子碰撞破坏的状态。此外，该器件的制造方法具有：通过使用离子辅助蒸发法以第一生长速度在构成光半导体器件的层叠体的光入射面或出射面上形成中间膜的第一工序，第二工序通过使用离子辅助蒸发法以比第一生长速度更低的生长速率在中间膜上形成保护膜的步骤。版权所有（C）2004，JPO

7. 发明专利

JP2003297926A Interdigital capacitor and method for adjusting its capacity 有权
标题翻译： INTERDIGITAL CAPACITOR AND METHOD FOR ADJUSTING ITS CAPACITY
公开(公告)号：JP2003297926A
公开(公告)日：2003-10-17
申请号：JP2002093377
申请日：2002-03-28
申请人： Fujitsu Quantum Devices Ltd , 富士通カンタムデバイス株式会社
发明人： MIYAZAWA NAOYUKI
IPC分类号： H01G4/255 , H01L21/822 , H01L23/522 , H01L27/04 , H01L27/08 , H03H3/10 , H03H9/145
CPC分类号： H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide an interdigital capacitor that can precisely adjust its capacity at a high frequency band of more than several tens of GHz, as well as a method for adjusting its capacity. SOLUTION: The capacitor includes a pair of comb-shaped electrodes (30 1 and 30 2 ) connected to signal lines plus at least one comb-shaped electrode (30 1 or 30 2 ) that is disconnected from the pair of comb-shaped electrodes and is not electrically connected to the signal lines. The capacity of the interdigital capacitor is adjusted by disconnecting the comb-shaped electrodes. The parts to be disconnected are provided as parts for disconnection, i.e., as parts different from the other comb-shaped electrodes. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种能够在高于几十GHz的高频带上精确地调整其容量的叉指电容器，以及用于调整其容量的方法。电容器包括连接到信号线加上至少一个梳状电极（30）的一对梳状电极（30 1 和30 2 ）（SB> 1 或30 2 ），其与该对梳状电极断开并且未电连接到信号线。通过断开梳状电极来调整交叉指状电容器的容量。要断开的部件被提供为用于断开的部分，即作为与其它梳状电极不同的部分。版权所有（C）2004，JPO

8. 发明专利

JP2000077651A Compound semiconductor device and its manufacture 失效
标题翻译：化学半导体器件及其制造
公开(公告)号：JP2000077651A
公开(公告)日：2000-03-14
申请号：JP21783398
申请日：1998-07-31
申请人： Fujitsu Quantum Device Kk , 富士通カンタムデバイス株式会社
发明人： IGARASHI TSUTOMU , ARIMOCHI KENJI , YOKOYAMA TERUO , MITANI EIZO , KURODA SHIGERU , NIKAIDOU JIYUNICHIROU , TATENO YASUNORI
IPC分类号： H01L29/872 , H01L21/338 , H01L29/10 , H01L29/47 , H01L29/778 , H01L29/812 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L31/112
CPC分类号： H01L29/7783 , H01L29/1029
摘要： PROBLEM TO BE SOLVED: To scarcely generate a walkout phenomenon, improve the breakdown voltage, and maintain the power applying efficiency to be high in a transistor wherein the length of the recess of a region between a gate electrode and a contact layer is at most 1 μm, in a field-effect transistor having high electron mobility.
SOLUTION: The concentration of impurities contained in a layer on an electron supply layer of a field-effect transistor having high electron mobility is set in a range of 1×1016-1×1017 atoms/cm3, or the band gap of a Schottky layer is wider than that of the electron supply layer, or a process wherein a GaAs burried layer 7 is heated after a silicon nitride layer 12 is formed on the GaAs burried layer 7 in which a second recess 14 is formed in a region inside a first recess 11 formed in a GaAs contact layer 9, is a step contained in a manufacturing process of the field-effect transistor having high electron mobility.
COPYRIGHT: (C)2000,JPO
摘要翻译：要解决的问题：为了几乎不产生罢工现象，提高击穿电压，并且在栅电极和接触层之间的区域的凹部的长度为至多1的晶体管中保持高的功率施加效率在具有高电子迁移率的场效应晶体管中。解决方案：具有高电子迁移率的场效应晶体管的电子供给层上的层中所含杂质的浓度设定在1×1016-1×1017原子/ cm3的范围内，或肖特基层的带隙比电子供给层宽，或者在形成有氮化硅层12的GaAs埋层7之后，在形成有第二凹部14的第一凹部内的区域内形成GaAs埋层7的工序 11形成在GaAs接触层9中，是包含在具有高电子迁移率的场效应晶体管的制造过程中的步骤。

9. 发明专利

JPH11274409A Semiconductor device, its manufacture and its etching method 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：JPH11274409A
公开(公告)日：1999-10-08
申请号：JP6904398
申请日：1998-03-18
申请人： Fujitsu Quantum Device Kk , 富士通カンタムデバイス株式会社
发明人： NUNOKAWA MITSUJI , SATO YUTAKA
IPC分类号： H01L27/04 , H01L21/306 , H01L21/822 , H01L27/095
摘要： PROBLEM TO BE SOLVED: To simultaneously form a source opening part and an element separation opening part by wet-etching by a method wherein, in a capacitor, a lower electrode formed at a first height level on a substrate is further extended to a second height level, and a dielectric film and an upper electrode are formed in this order on the lower electrode.
SOLUTION: A recess part 21A is formed on a substrate 21, and a lower electrode layer and a SiN film are respectively formed so as to cover the recess part 21A, and an upper electrode 25 is formed in a part covering the recess part 21a out of the SiN film. Next, a capacitor C comprising a SiO
2 pattern 22A, a lower electrode 23A and a SiN capacitor dielectric film 24A is formed on the substrate 21. A lower electrode pattern 23A of the capacitor C is formed so as to extend to the outside of the recess part 21A, namely onto a main face of the substrate 21. A thickness of the lower electrode layer, the SiN film and the upper electrode 25 is set so that an upper main face of the upper electrode 25 is set to the substantially same height as an upper main face of a part extending to the outside of the recess 21A out of the lower electrode pattern 23A.
COPYRIGHT: (C)1999,JPO
摘要翻译：要解决的问题：通过湿法蚀刻同时形成源极开口部分和元件分离开口部分，其中在电容器中，形成在衬底上的第一高度水平的下电极进一步延伸到第二高度电平，并且电介质膜和上电极依次形成在下电极上。解决方案：在基板21上形成凹部21A，分别形成下电极层和SiN膜以覆盖凹部21A，并且在覆盖凹部21a的部分形成上电极25 的SiN膜。接下来，在基板21上形成包括SiO 2图案22A，下电极23A和SiN电容器电介质膜24A的电容器C.电容器C的下电极图案23A形成为延伸到凹部的外侧部分21A，即在基板21的主面上。下电极层，SiN膜和上电极25的厚度被设定为使得上电极25的上主面被设定为与从下电极图案23A延伸到凹部21A的外侧的部分的上主面。

10. 发明专利

JP2004112178A Transmission line and device including the same 审中-公开
公开(公告)号：JP2004112178A
公开(公告)日：2004-04-08
申请号：JP2002270037
申请日：2002-09-17
申请人： Fujitsu Quantum Devices Ltd , 富士通カンタムデバイス株式会社
发明人： TSUKAJIMA KOJI
IPC分类号： H01L23/12 , H01L23/66 , H01P1/04 , H01P5/08 , H05K1/11
CPC分类号： H01L23/66 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2223/6627 , H01L2224/05554 , H01L2224/45014 , H01L2224/45144 , H01L2224/48091 , H01L2224/49175 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01039 , H01L2924/01079 , H01L2924/1903 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01P1/047 , H01L2924/00014 , H01L2924/00 , H01L2924/00015
摘要： PROBLEM TO BE SOLVED: To provide a transmission line for improving discontinuity of impedance caused between a device and the transmission line and to provide a device including the same.
SOLUTION: A configuration wherein the device 10 and a transmission line board 20a are connected by a gold wire 31, includes a ground pattern 23a integrally formed with two areas A in parallel with a signal line 22, and an area on a transmission line board 21 and placed between the signal line 22 and the device 10, in other words, an area B on the transmission line board 21 and between the gold wire 31 extended from the signal line 22 and the transmission line board 21. Thus, a capacitance C2 in parallel with a capacitance C1 formed between the gold wire 31 and an enclosure 30 is formed to enhance the impedance matching between an interface and a transmission line.
COPYRIGHT: (C)2004,JPO

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