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1. 发明专利

JP4490630B2 Method of erasing a non-volatile memory 有权
公开(公告)号：JP4490630B2
公开(公告)日：2010-06-30
申请号：JP2002570309
申请日：2001-12-28
申请人：ヘイロエルエスアイインコーポレイテッド
发明人：正気小椋 , 朋也斉藤 , 豊林
IPC分类号： H01L21/8247 , G11C16/02 , G11C16/14 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/14

2. 发明专利

JP4545256B2 Integrated method of sidewall split gate flash transistor 有权
公开(公告)号：JP4545256B2
公开(公告)日：2010-09-15
申请号：JP31125099
申请日：1999-11-01
申请人：ヘイロエルエスアイインコーポレイテッド
发明人：オグラセイキ
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/11517 , H01L27/11536 , H01L27/11541 , H01L29/66825
摘要： A fabrication method for an electrically programmable read only memory device, which consists of a control/word gate and a floating gate on the side wall of the control gate. The unique material selection and blocking mask sequences allow simple and safe fabrication within the delicate scaled CMOS process environment, of a side wall floating gate with an ultra short channel under the floating gate, which involves double side wall spacer formation i.e., a disposable side wall spacer and the final polysilicon spacer gate.

3. 发明专利

JP4422944B2 Monos memory array 有权
公开(公告)号：JP4422944B2
公开(公告)日：2010-03-03
申请号：JP2002086923
申请日：2002-03-26
申请人：ヘイロエルエスアイインコーポレイテッド
发明人：オグラトモコ , 公博佐藤 , 正気小椋 , 朋也斉藤
IPC分类号： H01L21/8247 , G11C11/34 , H01L21/3205 , H01L21/336 , H01L21/8238 , H01L21/8246 , H01L23/52 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833 , H01L2924/0002 , H01L2924/00
摘要： A middle resistive layer (041) is periodically connected to a conductive layer (061) and a second resistive layer (042) is periodically connected to this conductive layer to connect the bottom resistive layer (003) to the upper conductive layer (081). Use of only three metal layers (061,071,081) reduces the metal pitches and select transistors can be used to reduce the overall capacitance of the bit lines. An independent claim is included for a stitched metal/polysilicon oxide nitride oxide silicon memory array.

4. 发明专利

JP2010021572A Twin monos memory array structure 审中-公开
标题翻译： TWIN MONOS记忆阵列结构
公开(公告)号：JP2010021572A
公开(公告)日：2010-01-28
申请号：JP2009240354
申请日：2009-10-19
申请人： Halo Lsi Inc , ヘイロエルエスアイインコーポレイテッド
发明人： OGURA SEIKI , OGURA TOMOKO , SAITO TOMOYA
IPC分类号： G11C16/06 , H01L21/8247 , G11C16/02 , G11C16/04 , G11C16/14 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/14 , G11C16/0475
摘要： PROBLEM TO BE SOLVED: To improve an erase speed of a twin MONOS cell by applying a negative voltage to a word gate adjacent to a control gate in a selected memory and changing the distribution of high energy holes generated on a junction end portion under the control gate of the memory. SOLUTION: When Vword=0, an erasing target voltage Vt arrives at 0.5 V after one second. When the word gate is slightly biased to minus potential such as Vword=-0.5 V, an erase speed is increased almost to 1,000 times as large. This is because holes generated due to an inter-band tunnel effect are attracted to the word gate by negative potential on the junction end portion of a right diffusion region 42 and further accumulated under a target control gate 62. Further, the erase speed is increased equal to or more than 1,000 times as large by applying negative voltage of -1 V to the word gate. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了通过向选择的存储器中与控制栅极相邻的字门施加负电压并改变在连接端部分上产生的高能量空穴的分布来提高双MONOS电池的擦除速度在记忆的控制门下。解决方案：当Vword = 0时，一秒钟后擦除目标电压Vt达到0.5V。当字门稍微偏置到负电位（例如Vword = -0.5V）时，擦除速度几乎增加到1000倍。这是因为由于带内隧道效应而产生的空穴被右扩散区域42的接合端部的负电位吸引到字栅，并且进一步积累在目标控制栅极62的下方。此外，擦除速度增加通过对字门施加-1V的负电压等于或大于1,000倍。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP4262941B2 Addressing method and apparatus, a storage site reading method and apparatus, the programming method and apparatus, as well as erasing method and apparatus in cell units 有权
公开(公告)号：JP4262941B2
公开(公告)日：2009-05-13
申请号：JP2002197395
申请日：2002-07-05
申请人：ヘイロエルエスアイインコーポレイテッド
发明人：オグラトモコ , 正気小椋 , 朋也斉藤
IPC分类号： G11C16/02 , G11C16/06 , G11C16/04 , G11C16/08 , G11C16/14 , G11C16/24 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0475 , G11C16/08 , G11C16/14 , G11C16/24
摘要： In the present invention a twin MONOS metal bit line array is read and programmed using a three dimensional programming method with X, Y and Z dimensions. The word line address is the X address. The control gate line address is a function of the X and Z addresses, and the bit line address is a function of the Y and Z addresses. Because the bit lines and the control gate lines of the memory array are orthogonal a single cell can be erased with an adjacent memory, having the same selected bit and control gate lines, being inhibited from erase by application of the proper voltages to unselected word, control gate and bit lines.

6. 发明专利

JP4368087B2 Method of fabricating a twin monos cell 有权
公开(公告)号：JP4368087B2
公开(公告)日：2009-11-18
申请号：JP2002043294
申请日：2002-02-20
申请人：ヘイロエルエスアイインコーポレイテッド
发明人：公博佐藤 , 正気小椋 , 朋也斉藤
IPC分类号： H01L21/8247 , H01L21/336 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573 , H01L29/66833 , H01L29/7923 , Y10S257/906 , Y10S438/954
摘要： Presented in this invention is a high-density twin MONOS memory device integrating a twin MONOS memory cell array and CMOS logic device circuit and corresponding fabrication methods. Two aspects are described: i) Simultaneous definition of memory gate and logic gate, thus improving the process integration scheme for easier and more reliable fabrication. ii) Bit line crosses word gate and control gate (142). The invention focuses on lowering parasitic sheet resistances to enable high speed while maintaining low manufacturing cost. The twin MONOS cell stores memory in two nitride memory cell elements underlying two shared control gates on both sidewalls of a select gate. The method is applicable to a device with a flat channel and/or a device having a step channel.

7. 发明专利

JP4050048B2 Fast method of switching to the high-speed program and program verification 有权
公开(公告)号：JP4050048B2
公开(公告)日：2008-02-20
申请号：JP2001381765
申请日：2001-12-14
申请人：ヘイロエルエスアイインコーポレイテッド
发明人：オグラトモコ , オグラノリ , 正気小椋
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/12 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/3459 , G11C16/0475 , G11C16/12 , G11C16/3454
摘要： In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

8. 发明专利

JP2003036683A Twin monos memory cell usage for wide program 有权
标题翻译： TWIN MONOS MEMORY CELL USAGE FOR WIDE PROGRAM
公开(公告)号：JP2003036683A
公开(公告)日：2003-02-07
申请号：JP2002072030
申请日：2002-03-15
申请人： Halo Lsi Inc , ヘイロエルエスアイインコーポレイテッド
发明人： OGURA SEIKI , OGURA TOMOKO
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0475 , G11C16/10
摘要： PROBLEM TO BE SOLVED: To simultaneously select two nitride storage sites included in a MONOS memory cell for read, program and erase operation.
SOLUTION: A method of memory cell selection and operation to obtain wide program bandwidth and EEPROM erase capability. Two storage sites within a memory cell can be simultaneously selected during read, program and erase. By proper biasing, each of the sites can be independently read and programmed. Also, during program, the source of energy to reduce the current flow can be dynamically obtained from the storage charge on the selected bit line. If the bit line capacitance is not adequate to provide a charge that is necessary, additional bit line capacitance is borrowed from unselected bit line, or a source follower select transistor may be used.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：同时选择包括在MONOS存储单元中的两个氮化物存储位置进行读取，编程和擦除操作。解决方案：一种存储单元选择和操作的方法，以获得宽的程序带宽和EEPROM擦除能力。可以在读取，编程和擦除期间同时选择存储单元内的两个存储位置。通过适当的偏置，每个站点都可以独立读取和编程。此外，在程序期间，可以从所选位线上的存储电荷动态地获得用于减少电流的能量源。如果位线电容不足以提供必要的电荷，则可以从未选择的位线借用附加的位线电容，或者可以使用源极跟随器选择晶体管。

9. 发明专利

JP4490631B2 Non-volatile memory and reading method and writing method thereof 有权
公开(公告)号：JP4490631B2
公开(公告)日：2010-06-30
申请号：JP2002578582
申请日：2001-12-28
申请人：ヘイロエルエスアイインコーポレイテッド
发明人：トモコオグラ , 正気小椋 , 朋也斉藤 , 豊林
IPC分类号： H01L21/8247 , G11C16/02 , G11C16/04 , H01L27/115 , H01L27/12 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , G11C16/0466 , G11C16/0475 , H01L27/12
摘要： In the present invention a nonvolatile memory array architecture can be realized by a fabrication process more compatible to an MOS logic fabrication process as compared with previous nonvolatile memory array architectures. Higher write and/or read speed is possible because of a lower bit line resistance. A high hard bit density near 4F is possible when a self-align contact technology and a border less contact technology are used. Connection regions are formed throughout the memory array comprising four cells that are connected to one bit line. The connection regions can be formed in the same processing step with opposite conductivity regions for economy of processing. Apluralityof memorycells are two dimensionally disposed in two different directions with connection regions, conductivebit lines extending in the first direction, conductive word lines extending in the second direction, and conductive control lines.

10. 发明专利

JP4422936B2 Erasing method of twin monos memory array 有权
公开(公告)号：JP4422936B2
公开(公告)日：2010-03-03
申请号：JP2001371370
申请日：2001-12-05
申请人：ヘイロエルエスアイインコーポレイテッド
发明人：オグラトモコ , 正気小椋 , 朋也斉藤
IPC分类号： G11C16/06 , H01L21/8247 , G11C16/02 , G11C16/04 , G11C16/14 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/14 , G11C16/0475
摘要： A twin MONOS memory erase is achieved by applying a positive bias to the bit diffusion and a negative bias to the control gate. The other word gate and substrate terminals are grounded. But the voltage of word gate channel adjacent to the control gate can dramatically influence erase characteristics and speed, due to the short control gate channel length, which is a few times of the carrier escape length. A negative voltage application onto the word gate enhances erase speed, whereas a positive channel potential under the word gate reduces erase speed. By effective biasing of the memory array, word line or even single memory cell level erase is possible without area penalty, as compared to erase blocking by triple well or physical block separations of prior art. Near F-N channel erase without substrate bias application and program disturb protection by word line voltage are also included.

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