专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2012018706A Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：JP2012018706A
公开(公告)日：2012-01-26
申请号：JP2010153979
申请日：2010-07-06
申请人： Winbond Electronics Corp , ウィンボンド・エレクトロニクス株式会社
发明人： KAMINAGA TAKEHIRO , YANO MASARU , YOSHIDA MUNEHIRO , AOKI MINORU , ARAKAWA KENICHI
IPC分类号： G11C16/02 , G11C16/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory capable of accurately controlling a shift amount of a threshold of a memory cell.SOLUTION: A semiconductor memory in the present invention comprises: a memory cell array 100 including multiple memory cells which are arranged in a form of matrix and are capable of accumulating an electric charge; row selection means for selecting a memory cell in a row direction of the memory cell array; and write control means for writing data by applying a write pulse to the memory cell selected by the row selection means. When the write control means applies at least first and second temporally-continued write pulses P1 and P2, the second write pulse P2 has a low-voltage width portion VpgmL lower than a voltage of the first write pulse 1, and a high-voltage width portion VpgmH higher than a voltage of the first write pulse.
摘要翻译：解决的问题：提供能够精确地控制存储单元的阈值的偏移量的半导体存储器。解决方案：本发明的半导体存储器包括：存储单元阵列100，其包括以矩阵形式排列并且能够积累电荷的多个存储单元; 行选择装置，用于选择存储单元阵列的行方向上的存储单元; 以及写入控制装置，用于通过向由行选择装置选择的存储单元施加写入脉冲来写入数据。当写入控制装置至少施加第一和第二时间连续写入脉冲P1和P2时，第二写入脉冲P2具有低于第一写入脉冲1的电压的低电压宽度部分VpgmL，并且高电压宽度部分VpgmH高于第一写入脉冲的电压。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2011253591A Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：JP2011253591A
公开(公告)日：2011-12-15
申请号：JP2010126880
申请日：2010-06-02
申请人： Winbond Electronics Corp , ウィンボンド・エレクトロニクス株式会社
发明人： YANO MASARU , YOSHIDA MUNEHIRO , AOKI MINORU , ARAKAWA KENICHI
IPC分类号： G11C16/02 , G11C16/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory capable of reducing capacity interference between memory cells and writing data in a short period of time.SOLUTION: The semiconductor memory 10 has: a memory cell array which includes nonvolatile memory cells arranged in a matrix shape and can store i value data, and in which a plurality of memory cells are connected in series to form one cell unit, each unit cell is connected to a bit line in a corresponding column direction, and a memory cell in a row direction is connected to a corresponding word line; selecting means for selecting a page; holding means for holding write data; and write control means for using the write data held by the holding means to perform writing on the selected page. The write control means has a DBL write sequence for performing writing on the selected page, and an Oneway write sequence for dividing the selected page into a plurality of groups after the DBL write sequence, and performing writing on each divided group.
摘要翻译：要解决的问题：提供能够在短时间内减少存储单元之间的容量干扰并写入数据的半导体存储器。解决方案：半导体存储器10具有：存储单元阵列，其包括以矩阵形状排列并且可以存储i值数据的非易失性存储单元，并且其中多个存储器单元串联连接以形成一个单元单元，每个单位单元被连接到相应列方向上的位线，并且行方向上的存储单元连接到对应的字线; 用于选择页面的选择装置; 用于保存写入数据的保持装置; 以及写入控制装置，用于使用由保持装置保存的写入数据在所选择的页面上执行写入。写入控制装置具有用于在所选择的页面上执行写入的DBL写入序列和用于在DBL写入序列之后将所选择的页面分成多个组的单向写入序列，并且对每个划分的组执行写入。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2012027979A Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：JP2012027979A
公开(公告)日：2012-02-09
申请号：JP2010165951
申请日：2010-07-23
申请人： Winbond Electronics Corp , ウィンボンド・エレクトロニクス株式会社
发明人： AOKI MINORU , YANO MASARU
IPC分类号： G11C16/02
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory which can decrease threshold distribution width after deletion.SOLUTION: A semiconductor memory according to the present invention includes: a memory cell array which includes memory cells arranged in a matrix and in which multiple cell units configured by connecting the memory cells in series are formed; erasing means which applies an erasure voltage to a selected memory cell and erases data accumulated in the memory cell; verification means which verifies an erasure state of the selected memory cell; and erasure voltage determination means which determines an erasure voltage to be applied by the erasing means. The verification means includes verification before deletion and verification after deletion. When the verification after deletion is failed, the erasure voltage determination means determines the voltage of a erasure pulse which is applied next in response to the verification result of the verification before deletion.
摘要翻译：要解决的问题：提供可以减少删除之后的阈值分布宽度的半导体存储器。解决方案：根据本发明的半导体存储器包括：存储单元阵列，其包括以矩阵形式布置的存储单元，其中形成通过串联连接存储单元而配置的多个单元单元; 擦除装置，其将擦除电压施加到所选择的存储单元并擦除存储在存储单元中的数据; 验证装置，其验证所选存储单元的擦除状态; 以及擦除电压确定装置，其确定由擦除装置施加的擦除电压。验证手段包括删除后的验证和删除后的验证。当删除后的验证失败时，擦除电压确定装置响应于删除之前的验证的验证结果来确定下一次应用的擦除脉冲的电压。版权所有（C）2012，JPO＆INPIT

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式