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1. 发明申请

WO2020263365A1 MULTI-TAP DECISION FEEDBACK EQUALIZER (DFE) ARCHITECTURE WITH SPLIT-PATH SUMMER CIRCUITS 审中-公开
公开(公告)号：WO2020263365A1
公开(公告)日：2020-12-30
申请号：PCT/US2020/023214
申请日：2020-03-17
申请人： INTEL CORPORATION
发明人： DONG, Yikui , LI, Shenggao
IPC分类号： H04L25/03 , H04L25/49
摘要： Embodiments include apparatuses, methods, and systems including a decision feedback equalizer (DFE). The DFE includes a first summer circuit, a second summer circuit, a decision circuit, and a tap-delay line including a number of delay elements. The first summer circuit is to add together an analog signal and a first set of weighted feedback taps {h(j+1), h(m)} of time delayed signals of a detected symbol to generate a first summand. The second summer circuit is to add together a second set of weighted feedback taps {h(k+1),.. h(n)} of time delayed signals of the detected symbol to generate a second summand. The decision circuit is to receive at least the first summand and the second summand, to generate the detected symbol based on a sum including the first summand and the second summand. Other embodiments may also be described and claimed.

2. 发明申请

WO2019133013A1 SOURCE TO CHANNEL JUNCTION FOR III-V METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTORS (MOSFETS) 审中-公开
公开(公告)号：WO2019133013A1
公开(公告)日：2019-07-04
申请号：PCT/US2017/069149
申请日：2017-12-30
申请人： INTEL CORPORATION , HUANG, Cheng-Ying , RACHMADY, Willy , METZ, Matthew, V. , DEWEY, Gilbert , MA, Sean, T. , KAVALIEROS, Jack, T.
发明人： HUANG, Cheng-Ying , RACHMADY, Willy , METZ, Matthew, V. , DEWEY, Gilbert , MA, Sean, T. , KAVALIEROS, Jack, T.
IPC分类号： H01L29/78 , H01L29/66 , H01L29/10
摘要： Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate, and a channel area above the substrate and including a first III-V material. A source area may be above the substrate and including a second III-V material. An interface between the channel area and the source area may include the first III-V material. The source area may include a barrier layer of a third III-V material above the substrate. A current is to flow between the source area and the channel area through the barrier layer. Other embodiments may be described and/or claimed.

3. 发明申请

WO2018125492A1 VOLTAGE NOISE REDUCTION OF POWER DELIVERY NETWORKS FOR INTEGRATED CIRCUITS 审中-公开
公开(公告)号：WO2018125492A1
公开(公告)日：2018-07-05
申请号：PCT/US2017/063717
申请日：2017-11-29
申请人： INTEL CORPORATION
发明人： HUANG, Jimmy Huat Since , CAI, Xingjian , ONG, Paik Wen , CHEN, Herh Nan , JI, Yun
IPC分类号： H01L27/06 , H01L23/52
摘要： An electronic apparatus and an electronic system may include a first power delivery network (PDN) and a second PDN. The first PDN may include a first inductor as a segment of a power rail of the first PDN, while the second PDN may include a second inductor as a segment of a power rail of the second PDN. The first inductor and the second inductor may form a magnetically coupled inductor. The magnetically coupled inductor may provide migrated impedance Z T to the first PDN induced by the magnetically coupled inductor. The migrated impedance Z T to the first PDN may help the first PDN to reduce its voltage noise. Other embodiments may be described and/or claimed.

4. 发明申请

WO2018125140A1 METAL OXIDE THIN FILM TRANSISTORS WITH CONTROLLED HYDROGEN 审中-公开
公开(公告)号：WO2018125140A1
公开(公告)日：2018-07-05
申请号：PCT/US2016/069213
申请日：2016-12-29
申请人： INTEL CORPORATION
发明人： AHMED, Khaled
IPC分类号： H01L29/786 , H01L21/02 , H01L21/768
CPC分类号： H01L29/4908 , H01L27/1248 , H01L29/66969 , H01L29/7869
摘要： Embodiments herein describe techniques for a semiconductor device including a HDB layer protecting the channel layer of a TFT from hydrogen diffusion, e.g., from the gate dielectric layer. Embodiments may include a substrate, and a gate electrode above the substrate. A gate dielectric layer may conformally cover the gate electrode and the substrate. A HDB layer may be above the gate dielectric layer, and a channel layer may be above the HDB layer. Hence, the HDB layer may be between the gate dielectric layer and the channel layer, reducing the hydrogen diffusion from the gate dielectric layer to the channel layer. For a channel layer, TiO 2 , Al 2 O 3 , AlN, doped-TiO 2 , or doped-Al 2 O 3 , may be selected as a material for the HDB layer. Other embodiments may be described and/or claimed.

5. 发明申请

WO2018118337A1 WAVEGUIDE COMMUNICATION WITH INCREASED LINK DATA RATE 审中-公开
公开(公告)号：WO2018118337A1
公开(公告)日：2018-06-28
申请号：PCT/US2017/063058
申请日：2017-11-22
申请人： INTEL CORPORATION
发明人： DOGIAMIS, Georgios C. , KAMGAING, Telesphor , COHEN, Emanuel , OSTER, Sasha N.
IPC分类号： H04B10/2575 , H04B10/2507 , H04B3/52
摘要： Embodiments of the present disclosure may relate to a transceiver to transmit and receive concurrently radio frequency (RF) signals via a dielectric waveguide. In embodiments, the transceiver may include a transmitter to transmit to a paired transceiver a channelized radio frequency (RF) transmit signal via the dielectric waveguide. A receiver may receive from the paired transceiver a channelized RF receive signal via the dielectric waveguide. In embodiments, the channelized RF receive signal may include an echo of the channelized RF transmit signal. The transceiver may further include an echo suppression circuit to suppress from the channelized RF receive signal the echo of the channelized RF transmit signal. In some embodiments, the channelized RF transmit signal and the channelized RF receive signal may be within a frequency range of approximately 30 gigahertz (GHz) to approximately 1 terahertz (THz), and the transceiver may provide full-duplex millimeter-wave communication.

6. 发明申请

WO2018111447A3 OPTICAL MICRO MIRROR ARRAYS 审中-公开
公开(公告)号：WO2018111447A3
公开(公告)日：2018-06-21
申请号：PCT/US2017/060588
申请日：2017-11-08
申请人： INTEL CORPORATION
发明人： GROVER, Ginni , OSTER, Sasha N. , EID, Feras , HUNTER, Seth E.
IPC分类号： G02B5/02 , G02B1/10
摘要： Embodiments include techniques and configurations for apparatuses and methods for making an optical imaging device based on a micro mirror array. The method may include forming an array of trenches in a substrate. The array of trenches may be formed by intersecting a first plurality of walls with a second plurality of walls in the substrate. A trench of the array of trenches may be formed by adjacent walls of the first plurality of walls and intersecting adjacent walls of the second plurality of walls. A wall of the trench may include a side surface coupled with a top surface. A reflective layer may be deposited conformally to cover the side surface of the wall and to serve as a reflector. A supporting layer may be formed above the substrate, or within the array of trenches, to provide mechanical support for the array of trenches. Other embodiments may be claimed.

7. 发明申请

WO2018111226A1 TRANSISTOR WITH ASYMMETRIC THRESHOLD VOLTAGE CHANNEL 审中-公开
公开(公告)号：WO2018111226A1
公开(公告)日：2018-06-21
申请号：PCT/US2016/066232
申请日：2016-12-12
申请人： INTEL CORPORATION
发明人： LEE, Chen-guan , CHANG, Hsu-yu , PARK, Joodong , HAFEZ, Walid M. , JAN, Chia-hong
IPC分类号： H01L29/78 , H01L29/66
摘要： Embodiments herein describe techniques for a transistor including a drain, a source, and a channel between the drain and the source. The channel may include a first channel portion and a second channel portion adjacent to the first channel portion. The transistor may include a gate, wherein the gate may include a first gate portion and a second gate portion, where the first gate portion may include a first metal, and the second gate portion may include a second metal different from the first metal. The first gate portion may overlap the first channel portion, and the first gate portion and the second gate portion may overlap the second channel portion.

8. 发明申请

WO2018063634A1 THERMAL INTERFACES FOR INTEGRATED CIRCUIT PACKAGES 审中-公开
标题翻译：集成电路封装的热界面
公开(公告)号：WO2018063634A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/048846
申请日：2017-08-28
申请人： INTEL CORPORATION
发明人： CETEGEN, Edvin , KARHADE, Omkar G. , DHANE, Kedar , JHA, Chandra M.
IPC分类号： H01L23/367 , H01L23/373 , H01L23/00 , H01L25/065 , H01L23/40
摘要： A thermal interface may include a wired network made of a first TIM, and a second TIM surrounding the wired network. A heat spreader lid may include a wired network attached to an inner surface of the heat spreader lid. An IC package may include a heat spreader lid placed over a first electronic component and a second electronic component. A first thermal interface may be formed between the first electronic component and the inner surface of the heat spreader lid, and a second thermal interface may be formed between the second electronic component and the inner surface of the heat spreader lid. The first thermal interface may include a wired network of a first TIM surrounded by a second TIM, while the second thermal interface may include the second TIM, without a wired network of the first TIM. Other embodiments may be described and/or claimed.
摘要翻译：热接口可以包括由第一TIM构成的有线网络和围绕有线网络的第二TIM。散热器盖可以包括附接到散热器盖的内表面的有线网络。 IC封装可以包括放置在第一电子部件和第二电子部件上的散热器盖。第一热界面可以形成在第一电子部件和散热器盖的内表面之间，并且第二热界面可以形成在第二电子部件和散热器盖的内表面之间。第一热接口可以包括由第二TIM围绕的第一TIM的有线网络，而第二热接口可以包括第二TIM，而不具有第一TIM的有线网络。其他实施例可以被描述和/或要求保护。

9. 发明申请

WO2018004700A1 TRANSISTORS WITH METAL SOURCE AND DRAIN CONTACTS INCLUDING A HEUSLER ALLOY 审中-公开
标题翻译：晶体管与金属源和漏极接触，包括HEUSLER合金
公开(公告)号：WO2018004700A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040877
申请日：2016-07-01
申请人： INTEL CORPORATION
发明人： MANIPATRUNI, Sasikanth , ANURAG, Chaudhry , NIKONOV, Dmitri E. , CHAWLA, Jasmeet S. , WIEGAND, Christopher J. , KANWALJIT, Singh , AVCI, Uygar E. , YOUNG, Ian A.
IPC分类号： H01L29/78 , H01L21/8238 , H01L29/66
CPC分类号： H01L29/66984 , B82Y10/00 , H01L21/28537 , H01L21/28581 , H01L29/0669 , H01L29/0673 , H01L29/1054 , H01L29/16 , H01L29/20 , H01L29/24 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/452 , H01L29/456 , H01L29/47 , H01L29/475 , H01L29/66356 , H01L29/66439 , H01L29/66469 , H01L29/7391 , H01L29/775 , H01L29/7849 , H01L29/785 , H01L29/78654 , H01L29/78681
摘要： Embodiments herein describe techniques for a semiconductor device comprising a channel having a first semiconductor material; a source contact coupled to the channel, comprising a first Heusler alloy; and a drain contact coupled to the channel, comprising a second Heusler alloy. The first Heusler alloy is lattice-matched to the first semiconductor material within a first predetermined threshold. A first Schottky barrier between the channel and the source contact, and a second Schottky barrier between the channel and the drain contact are negative, or smaller than another predetermined threshold. The source contact and the drain contact can be applied to a strained silicon transistor, an III-V transistor, a tunnel field-effect transistor, a dichalcogenide (MX2) transistor, and a junctionless nanowire transistor.
摘要翻译：这里的实施例描述了用于包括具有第一半导体材料的沟道的半导体器件的技术; 耦合到所述通道的源极触点，包括第一赫斯勒合金; 以及耦合到通道的漏极触点，其包括第二赫斯勒合金。第一赫斯勒合金在第一预定阈值内与第一半导体材料晶格匹配。沟道与源极接触之间的第一肖特基势垒以及沟道与漏极接触之间的第二肖特基势垒是负的或小于另一预定阈值。源极触点和漏极触点可应用于应变硅晶体管，III-V晶体管，隧道场效应晶体管，二硫族化合物（MX2）晶体管和无结纳米线晶体管。

10. 发明申请

WO2019132985A1 III-V TRANSISTORS WITH RESISTIVE GATE CONTACTS 审中-公开
公开(公告)号：WO2019132985A1
公开(公告)日：2019-07-04
申请号：PCT/US2017/068996
申请日：2017-12-29
申请人： INTEL CORPORATION , RADOSAVLJEVIC, Marko , DASGUPTA, Sansaptak , THEN, Han Wui
发明人： RADOSAVLJEVIC, Marko , DASGUPTA, Sansaptak , THEN, Han Wui
IPC分类号： H01L29/78 , H01L29/778 , H01L29/10 , H01L29/66
摘要： Embodiments herein describe techniques, systems, and method for a semiconductor device that may include an III-V transistor with a resistive gate contact. A semiconductor device may include a substrate, and a channel base including a layer of GaN above the substrate. A channel stack may be above the channel base, and may include a layer of GaN in the channel stack, and a polarization layer above the layer of GaN in the channel stack. A gate stack may be above the channel stack, where the gate stack may include a gate dielectric layer above the channel stack, and a resistive gate contact above the gate dielectric layer. The resistive gate contact may include silicon (Si) or germanium (Ge). Other embodiments may be described and/or claimed.

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