专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2017052616A1 ISOLATION STRUCTURES FOR AN INTEGRATED CIRCUIT ELEMENT AND METHOD OF MAKING SAME 审中-公开
标题翻译：集成电路元件的隔离结构及其制造方法
公开(公告)号：WO2017052616A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052324
申请日：2015-09-25
申请人： INTEL CORPORATION
发明人： LILAK, Aaron, D. , AVCI, Uygar, E. , KENCKE, David, L. , MORROW, Patrick , FOLEY, Kerryann , CEA, Stephen, M. , MEHANDRU, Rishabh
IPC分类号： H01L27/12
CPC分类号： H01L29/41791 , H01L21/845 , H01L27/1211
摘要： Techniques and mechanisms to provide insulation for a component of an integrated circuit device. In an embodiment, structures of a circuit component are formed in or on a first side of a semiconductor substrate, the structures including a first doped region, a second doped region and a third region between the first doped region and the second doped region. The substrate has formed therein an insulation structure, proximate to the circuit component structures, which is laterally constrained to extend only partially from a location under the circuit component toward an edge of the substrate. In another embodiment, a second side of the substrate − opposite the first side − is exposed by thinning to form the substrate from a wafer. Such thinning enables subsequent back side processing to form a recess in the second side, and to deposit the insulation structure in the recess.
摘要翻译：为集成电路器件的元件提供绝缘的技术和机制。在一个实施例中，电路部件的结构形成在半导体衬底的第一侧中或其上，该结构包括第一掺杂区域，第二掺杂区域和第一掺杂区域和第二掺杂区域之间的第三区域。衬底在其中形成有绝缘结构，靠近电路部件结构，该绝缘结构被横向限制为仅部分地从电路部件下方的位置朝向衬底的边缘延伸。在另一个实施例中，衬底的与第一侧相对的第二侧通过变薄暴露以从晶片形成衬底。这种变薄使得后续的后续处理能够在第二侧中形成凹槽，并且将绝缘结构沉积在凹部中。

2. 发明申请

WO2016191437A1 DEVICE, APPARATUS AND SYSTEM TO REDUCE CURRENT LEAKAGE DURING DIFFERENTIAL COMMUNICATIONS 审中-公开
标题翻译：在差异通信中减少电流泄漏的装置，装置和系统
公开(公告)号：WO2016191437A1
公开(公告)日：2016-12-01
申请号：PCT/US2016/033975
申请日：2016-05-24
申请人： INTEL CORPORATION
发明人： THANIGASALAM, Haran , PETERSON, Steven
IPC分类号： H04N21/2343 , H04N21/242 , H04N21/25 , H04N19/30
CPC分类号： H04L25/0272
摘要： Techniques and mechanisms for communicating packets of image information, the packets each having a respective format that is defined or otherwise indicated by a camera serial interface standard. In an embodiment, circuitry of a first physical layer (PHY) is operated to facilitate such communication via a lane of an interconnect that is coupled between the first PHY and a second PHY. The PHYs further communicate between each other a packet delimiter sequence between two such packets. In another embodiment, the plurality of packets and the packet delimiter sequence are communicated after a transition of one PHY from a relatively low power state, and prior to any subsequent transition of that PHY back to the relatively low power state. The camera serial interface standard specifies or otherwise indicates a protocol whereby a transition to such a low power state is performed between the respective communications of any two successive packets.
摘要翻译：用于传送图像信息分组的技术和机制，每个分组具有由相机串行接口标准定义或以其它方式指示的相应格式的分组。在一个实施例中，第一物理层（PHY）的电路被操作以促进经由耦合在第一PHY和第二PHY之间的互连的通道的这种通信。 PHY进一步在两个这样的分组之间彼此通信分组定界符序列。在另一个实施例中，多个分组和分组定界符序列在一个PHY从相对低功率状态的转换之后，以及在该PHY的任何后续转换返回到相对低功率状态之后被传送。相机串行接口标准指定或以其它方式指示协议，由此在任何两个连续分组的相应通信之间执行向这样的低功率状态的转换。

3. 发明申请

WO2015094377A1 PHOTODETECTOR WITH TAPERED WAVEGUIDE STRUCTURE 审中-公开
标题翻译：带波纹波纹结构的光电转换器
公开(公告)号：WO2015094377A1
公开(公告)日：2015-06-25
申请号：PCT/US2013/077313
申请日：2013-12-20
申请人： INTEL CORPORATION , VINCENT, Benjamin , FESHALI, Avi
发明人： VINCENT, Benjamin , FESHALI, Avi
IPC分类号： H01L31/12
CPC分类号： H01L31/105 , G02B6/1228 , G02B6/4295 , G02B2006/121 , H01L31/02327 , H01L31/028 , H01L31/1804 , Y02E10/52
摘要： Techniques and mechanisms for providing efficient direction of light to a photodetector with a tapered waveguide structure. In an embodiment, a taper structure of a semiconductor device comprises a substantially single crystalline silicon. A buried oxide underlies and adjoins the monocrystalline silicon of the taper structure, and a polycrystalline Si is disposed under the buried oxide. During operation of the semiconductor device light is redirected in the taper structure and received via a first side of a Germanium photodetector. In another embodiment, one or more mirror structures positioned on a far side of the Germanium photodetector may provide for a portion of the light to be reflected back to the Germanium photodetector.
摘要翻译：用于向具有锥形波导结构的光电检测器提供有效的光线方向的技术和机构。在一个实施例中，半导体器件的锥形结构包括基本上单晶硅。掩埋氧化物位于锥形结构的单晶硅的下面并毗邻，并且多晶Si设置在掩埋氧化物的下方。在半导体器件的操作期间，光在锥形结构中重定向并经由锗光电检测器的第一侧接收。在另一个实施例中，位于锗光电探测器的远侧上的一个或多个反射镜结构可以将待反射的光的一部分返回到锗光电检测器。

4. 发明申请

WO2015047257A1 DEVICE, SYSTEM AND METHOD FOR PROVIDING MEMS STRUCTURES OF A SEMICONDUCTOR PACKAGE 审中-公开
标题翻译：用于提供半导体封装的MEMS结构的器件，系统和方法
公开(公告)号：WO2015047257A1
公开(公告)日：2015-04-02
申请号：PCT/US2013/061762
申请日：2013-09-25
申请人： INTEL CORPORATION , TEH, Weng Hong , IBRAHIM, Tarek A. , HANEY, Sarah K. , SOBIESKI, Daniel N. , ZANTYE, Parshuram B. , MAIR, Chad E. , KAMGAING, Telesphor
发明人： TEH, Weng Hong , IBRAHIM, Tarek A. , SOBIESKI, Daniel N. , ZANTYE, Parshuram B. , MAIR, Chad E. , KAMGAING, Telesphor
IPC分类号： H01L29/84
CPC分类号： B81C1/00246 , B81B2201/0271 , B81C1/00261 , B81C1/00277 , H01L21/568 , H01L24/19 , H01L2224/04105 , H01L2224/73267 , H01L2924/01079
摘要： Techniques and mechanisms for providing precisely fabricated structures of a semiconductor package. In an embodiment, a build-up carrier of the semiconductor package includes a layer of porous dielectric material. Seed copper and plated copper is disposed on the layer of porous dielectric material. Subsequent etching is performed to remove copper adjacent to the layer of porous dielectric material, forming a gap separating a suspended portion of a MEMS structure from the layer of porous dielectric material. In another embodiment, the semiconductor package includes a copper structure disposed between portions of an insulating layer or portions of a layer of silicon nitride material. The layer of silicon nitride material couples the insulating layer to another insulating layer. One or both of the insulating layers are each protected from desmear processing with a respective release layer structure.
摘要翻译：用于提供半导体封装的精确制造结构的技术和机构。在一个实施例中，半导体封装的积聚载体包括多孔介电材料层。种子铜和电镀铜设置在多孔电介质材料层上。进行随后的蚀刻以去除邻近多孔介电材料层的铜，形成将MEMS结构的悬置部分与多孔介电材料层分开的间隙。在另一个实施例中，半导体封装包括设置在绝缘层的一部分之间或者氮化硅材料层的一部分的铜结构。氮化硅材料层将绝缘层耦合到另一绝缘层。每个绝缘层中的一个或两个保护层不受去离子处理的剥离层结构的剥离。

5. 发明申请

WO2014085267A1 APPARATUS, METHOD AND SYSTEM FOR PROVIDING TERMINATION FOR MULTIPLE CHIPS OF AN INTEGRATED CIRCUIT PACKAGE 审中-公开
标题翻译：用于提供集成电路封装多个引脚的终止的装置，方法和系统
公开(公告)号：WO2014085267A1
公开(公告)日：2014-06-05
申请号：PCT/US2013/071533
申请日：2013-11-22
申请人： INTEL CORPORATION , VERGIS, George , BAINS, Kuljit S. , MCCALL, James A. , CHANG, Ge
发明人： VERGIS, George , BAINS, Kuljit S. , MCCALL, James A. , CHANG, Ge
IPC分类号： G11C11/40
CPC分类号： G11C11/4074 , G06F3/0604 , G06F3/0637 , G06F3/0673 , G06F13/1663 , G11C7/1057 , G11C7/1072 , G11C7/1084 , G11C7/109 , G11C8/06 , G11C11/408 , Y10T29/41
摘要： Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series
摘要翻译：用于为存储器件的多个芯片提供终端的技术和机制。在一个实施例中，存储器件是集成电路（IC）封装，其包括命令和地址总线以及与其耦合的多个存储器芯片。在多个存储器芯片中，只有第一存储器芯片可操作以选择性地提供对命令和地址总线的终止。在多个存储器芯片的各个片上终端控制电路中，仅第一存储器芯片的片上终端控制电路经由任何终端控制信号线耦合到任何输入/输出（I / O）触点 IC封装。在另一个实施例中，多个存储器芯片彼此串联配置，并且其中第一存储器芯片位于该系列的一端

6. 发明申请

WO2017171886A1 DEVICE AND METHOD FOR PROVIDING A MULTI-DISPLAY SYSTEM 审中-公开
标题翻译：用于提供多显示系统的装置和方法
公开(公告)号：WO2017171886A1
公开(公告)日：2017-10-05
申请号：PCT/US2016/025775
申请日：2016-04-02
申请人： INTEL CORPORATION
发明人： LAI, Min-Tih
IPC分类号： G06F3/14
CPC分类号： G06F3/1438 , G06F1/163 , G06F1/1637 , G06F1/1649 , G06F1/1656 , G06F1/1658
摘要： Techniques and mechanisms for providing functionality of a multi-display system. In an embodiment, a first device, including a first housing and a first display, is configured to couple to a second device which includes a second housing and a second display. During connectivity of the first device to the second device, a majority of an exterior volume of the first housing is disposed in a recess formed at least in part by the second housing. A host mode of the first device enables the first device to control the second display and/or other resources of the second device. Another mode of the first device enables operation of the first device as an independent mobile device.
摘要翻译：
提供多显示器系统功能的技术和机制。在一个实施例中，包括第一外壳和第一显示器的第一设备被配置为耦合到包括第二外壳和第二显示器的第二设备。在将第一装置连接到第二装置期间，第一壳体的大部分外部容积设置在至少部分由第二壳体形成的凹部中。第一设备的主机模式使得第一设备能够控制第二设备的第二显示器和/或其他资源。第一个设备的另一种模式可以将第一个设备作为独立的移动设备进行操作。

7. 发明申请

WO2017052645A1 METHOD, DEVICE AND SYSTEM TO PROVIDE CAPACITANCE FOR A DYNAMIC RANDOM ACCESS MEMORY CELL 审中-公开
标题翻译：用于为动态随机存取存储器提供电容的方法，装置和系统
公开(公告)号：WO2017052645A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052455
申请日：2015-09-25
申请人： INTEL CORPORATION
发明人： LILAK, Aaron , MORROW, Patrick , MEHANDRU, Rishabh , NELSON, Donald W. , CEA, Stephen M.
IPC分类号： H01L27/108
CPC分类号： H01L27/1087 , H01L27/1082 , H01L27/10832 , H01L27/10858 , H01L27/10867
摘要： Techniques and mechanisms to provide capacitance with a memory cell of an integrated circuit. In an embodiment, a transistor of the memory cell includes structures variously formed in or on a first side of a semiconductor substrate. After processing to form the transistor structures, thinning is performed to expose a second side of the semiconductor substrate, the second side opposite the first side. Processing in or on the exposed second side of the semiconductor substrate is subsequently performed to form in the semiconductor substrate a capacitor that extends to couple to one of the transistor structures. In another embodiment, the capacitor is coupled to accumulate charge based on activation of a channel of the transistor. The capacitor is further coupled to send charge from the memory cell via the second side.
摘要翻译：为集成电路的存储单元提供电容的技术和机制。在一个实施例中，存储单元的晶体管包括不同地形成在半导体衬底的第一侧上或其上的结构。在形成晶体管结构的处理之后，进行薄化以使半导体衬底的第二侧，与第一侧相对的第二面露出。随后在半导体衬底中在半导体衬底的暴露的第二侧中或之上进行加工，以在半导体衬底中形成延伸以耦合到晶体管结构之一的电容器。在另一个实施例中，电容器被耦合以基于晶体管的沟道的激活来累积电荷。电容器还被耦合以经由第二侧从存储器单元发送电荷。

8. 发明申请

WO2017052593A1 ARCHITECTURE TO COMMUNICATE SIGNALS FOR OPERATING A STATIC RANDOM ACCESS MEMORY 审中-公开
标题翻译：用于运行静态随机存取存储器的信号通信架构
公开(公告)号：WO2017052593A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052250
申请日：2015-09-25
申请人： INTEL CORPORATION
发明人： NELSON, Donald, W. , KARL, Eric, A.
IPC分类号： H01L27/11
CPC分类号： H01L27/1116 , G11C11/413 , H01L27/1104
摘要： Techniques and mechanisms for exchanging signals with one or more transistors at a front side of a semiconductor substrate. In an embodiment, an integrated circuit include a cell - such as a static random access memory (SRAM) cell - comprising transistor structures variously disposed in or on a first side of a substrate. After fabrication of such transistor structures, substrate material may be thinned to expose a second side of the substrate, opposite the first side. A first interconnect and a second interconnect are coupled each to exchange a signal or a voltage. In another embodiment, respective portions of the first interconnect and the second interconnect extend on opposite sides of the substrate, wherein the first side and the second side each extend between such interconnect portions. Positioning of interconnect structures on opposite sides of the substrate allow for performance improvements due to low interconnect resistances.
摘要翻译：用于与半导体衬底的前侧的一个或多个晶体管交换信号的技术和机制。在一个实施例中，集成电路包括诸如静态随机存取存储器（SRAM）单元的单元 - 包括不同地设置在衬底的第一侧中或其上的晶体管结构的单元。在制造这种晶体管结构之后，衬底材料可以变薄以暴露衬底的与第一侧相对的第二侧。第一互连和第二互连被耦合以交换信号或电压。在另一个实施例中，第一互连和第二互连的相应部分在衬底的相对侧上延伸，其中第一侧和第二侧各自在这种互连部分之间延伸。互连结构在衬底的相对侧上的定位允许由于低的互连电阻而导致的性能改进。

9. 发明申请

WO2013095569A1 METHOD, APPARATUS AND SYSTEM FOR SELECTIVE EXECUTION OF A COMMIT INSTRUCTION 审中-公开
标题翻译：方法，选择性执行委托指令的方法和系统
公开(公告)号：WO2013095569A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067021
申请日：2011-12-22
申请人： INTEL CORPORATION , CODINA, Enric Gibert , CODINA, Josep M. , LATORRE, Fernando , MARCUELLO, Pedro , LOPEZ, Pedro , GOMEZ REQUENA, Crispin , GONZALEZ, Antonio , HYUSEINOVA, Mirem , KOTSELIDIS, Christos E. , LUPON, Marc , GIMENO, Carlos Madriles , MAGKLIS, Grigorios , VICENTE, Alejandro Martinez , MARTINEZ, Raul , ORTEGA, Daniel , PAVLOU, Demos , STAVROU, Kyriakos A. , TOURNAVITIS, Georgios , XEKALAKIS, Polychronis
发明人： CODINA, Enric Gibert , CODINA, Josep M. , LATORRE, Fernando , MARCUELLO, Pedro , LOPEZ, Pedro , GOMEZ REQUENA, Crispin , GONZALEZ, Antonio , HYUSEINOVA, Mirem , KOTSELIDIS, Christos E. , LUPON, Marc , GIMENO, Carlos Madriles , MAGKLIS, Grigorios , VICENTE, Alejandro Martinez , MARTINEZ, Raul , ORTEGA, Daniel , PAVLOU, Demos , STAVROU, Kyriakos A. , TOURNAVITIS, Georgios , XEKALAKIS, Polychronis
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30087 , G06F9/30185 , G06F9/3842 , G06F9/3857 , G06F9/3863
摘要： Techniques and mechanisms for a processor to determine whether a commit action is to be performed. In an embodiment, a processor performs operations to determine whether a commit instruction is for contingent performance of a commit action. In another embodiment, one or more conditions of processor state are evaluated in response to determining that the commit instruction is for contingent performance of the commit action, where the evaluation is performed to determine whether the commit action indicated by the commit instruction is to be performed.
摘要翻译：处理器确定是否执行提交动作的技术和机制。在一个实施例中，处理器执行操作以确定提交指令是否用于或然执行提交动作。在另一个实施例中，响应于确定提交指令用于提交动作的或然执行来评估处理器状态的一个或多个条件，其中执行评估以确定是否要执行由提交指令指示的提交动作。

10. 发明申请

WO2013074106A1 METHOD, APPARATUS AND SYSTEM FOR DATA DEDUPLICATION 审中-公开
标题翻译：数据分类方法，装置和系统
公开(公告)号：WO2013074106A1
公开(公告)日：2013-05-23
申请号：PCT/US2011/061246
申请日：2011-11-17
申请人： INTEL CORPORATION , JONES, Marc T.
发明人： JONES, Marc T.
IPC分类号： G06F13/14 , G06F12/00
CPC分类号： G06F17/30156 , G06F3/061 , G06F3/0641 , G06F3/0659 , G06F3/067
摘要： Techniques and mechanisms for limiting storage of duplicate data in a storage back-end. In an embodiment, a storage device of the storage back-end receives from a storage front-end a write command specifying a write of data to the storage back-end. In another embodiment, the storage device calculates and provides to the storage front-end a data signature for data which is the subject of the write command. Based on the data signature provided by the storage device, a deduplication engine of the storage front-end determines whether a deduplication operation is to be performed.
摘要翻译：用于限制存储后端中重复数据的存储的技术和机制。在一个实施例中，存储后端的存储装置从存储前端接收指定对存储后端的数据写入的写入命令。在另一个实施例中，存储设备计算并向存储前端提供作为写命令对象的数据的数据签名。基于由存储装置提供的数据签名，存储前端的重复数据删除引擎确定是否执行重复数据删除操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式