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1. 发明申请

WO1990010559A1 SYSTEM FOR CONTROLLING A NUMBER OF AUTOMOTIVE ELECTRICAL DEVICES 审中-公开
标题翻译：用于控制多台汽车电气设备的系统
公开(公告)号：WO1990010559A1
公开(公告)日：1990-09-20
申请号：PCT/IT1990000023
申请日：1990-03-06
申请人： ROLTRA-MORSE S.P.A. , SGS-THOMSON MICROELECTRONICS S.R.L. , BRUSASCO, Enzo , BOERO, Giuseppe , STORTI, Sandro , MURARI, Bruno
发明人： ROLTRA-MORSE S.P.A. , SGS-THOMSON MICROELECTRONICS S.R.L.
IPC分类号： B60R16/02
CPC分类号： B60R16/0315 , B60R2016/0322
摘要： A system for controlling a number of electric devices (14, 15, 17, 18, 28, 28'; 19) on a car (1), particularly those fitted to the vehicle door (2, 2', 3, 3') and comprising at least a window regulator (18), a door lock device (17), a manual control push-button device (14) and a device (15) for electrically controlling an external rearview mirror (16); which devices (14, 15, 17, 18, 28, 28'; 19) comprise at least an electric operating member (24), and which system comprises at least a central processing unit (5) and at least a cable (7, 7', 8, 8') for electrically connecting the central processing unit (5) to the devices (14, 15, 17, 18, 28, 28'; 19); a single electric connecting cable (7, 7', 8, 8') being provided for the devices (14, 15, 17, 18) on each door (2, 2', 3, 3'), and comprising a first wire (10) for supplying positive electrical power, a second wire (11) for transmitting information signals, and a third ground wire (12); which information signals are transmitted over the aforementioned second wire (11) in asynchronous, serial manner; and which devices (14, 15, 17, 18, 28, 28'; 19) comprise a specific electronic control block (27) comprising at least a first integrated circuit (23) for supplying electrical power for operating the aforementioned member (24), and a second integrated circuit (25) for processing information signals relative to operation of the same.
摘要翻译：一种用于控制轿厢（1）上的多个电气设备（14,15,17,18,28,28'; 19）的系统，特别是安装在车门（2,2'，3'）上的那些装置并且至少包括窗口调节器（18），门锁装置（17），手动控制按钮装置（14）和用于电控制外部后视镜（16）的装置（15）。所述装置（14,15,17,18,28,28'; 19）至少包括电操作构件（24），并且该系统至少包括中央处理单元（5）和至少一个电缆（7，用于将中央处理单元（5）电连接到设备（14,15,17,18,28,28'; 19）上的7'，8,8'; 为每个门（2,2'，3,3'）上的设备（14,15,17,18）提供单个电连接电缆（7,7'，8,8'），并且包括第一线（10），用于发送正电力的第二电线（11）和用于发送信息信号的第二电线（11）和第三接地线（12）。哪些信息信号以异步串行方式在上述第二线路（11）上传输; 以及哪些装置（14,15,17,18,28,28'; 19）包括特定的电子控制块（27），该电子控制块包括用于提供用于操作上述构件（24）的电力的至少第一集成电路（23），以及用于处理相对于其操作的信息信号的第二集成电路（25）。

2. 发明申请

WO1997049087A1 MULTI-LEVEL MEMORY CIRCUIT WITH REGULATED READING VOLTAGE 审中-公开
标题翻译：具有规定读数电压的多级存储器电路
公开(公告)号：WO1997049087A1
公开(公告)日：1997-12-24
申请号：PCT/IT1996000198
申请日：1996-10-30
申请人： SGS-THOMSON MICROELECTRONICS S.R.L. , ROLANDI, Paolo
发明人： SGS-THOMSON MICROELECTRONICS S.R.L.
IPC分类号： G11C11/56
CPC分类号： G11C11/5621 , G11C5/145 , G11C11/5642 , G11C16/30
摘要： A multi-level memory circuit for binary information, according to the invention, comprises a plurality (MTX) of memory cells, each adapted to store more than one item of binary information and comprised of at least one floating gate MOS transistor, the information stored therein corresponding to the level of the cell threshold voltage, and a read voltage generating circuit (ALIM) for the cell plurality, adapted to be input a supply voltage (VCC). The generating circuit (ALIM) includes a voltage boosting circuit (CHP) adapted to generate a read voltage (VW) having a higher value than the value of the supply voltage (VCC).
摘要翻译：根据本发明的用于二进制信息的多级存储器电路包括多个（MTX）存储器单元，每个存储单元适于存储多于一个的二进制信息项，并且包括至少一个浮置栅极MOS晶体管，所存储的信息其中对应于单元阈值电压的电平，以及适用于输入电源电压（VCC）的单元多个的读取电压产生电路（ALIM）。发生电路（ALIM）包括适于产生具有比电源电压（VCC）的值更高的值的读取电压（VW）的升压电路（CHP）。

4. 发明申请

WO1997020320A1 MONOLITHICALLY INTEGRATED DEVICE 审中-公开
标题翻译：单一集成设备
公开(公告)号：WO1997020320A1
公开(公告)日：1997-06-05
申请号：PCT/IT1996000226
申请日：1996-11-26
申请人： SGS-THOMSON MICROELECTRONICS S.R.L. , MASTROMATTEO, Ubaldo
发明人： SGS-THOMSON MICROELECTRONICS S.R.L.
IPC分类号： G21B01/00
CPC分类号： G21B3/00 , G21B3/002 , Y02E30/18
摘要： The monolithically integrated device according to this invention comprises a first substrate (SUB) and, at least in a portion: a) a first structure (ST1) of a first material in solid form suitable to absorb hydrogen with ensuing generation of thermal energy, superposed to said substrate (SUB); b) a second structure (ST2) of a second material in solid form suitable to release hydrogen when it reaches a temperature higher than a prefixed temperature, superposed to said substrate (SUB); c) a third structure (ST3) of a third material in solid form suitable to generate thermal energy when it is submitted to the passage of electric current, so placed as to be thermally coupled at least to said second structure (ST2); wherein said first structure (ST1) and said second structure (ST2) are in contact, at least partly, with one another.
摘要翻译：根据本发明的单片集成器件包括第一衬底（SUB），并且至少部分地包括：a）固体形式的第一材料的第一结构（ST1），其适合于随后产生热能吸收氢，叠加到所述衬底（SUB）; b）固体形式的第二材料的第二结构（ST2），当其达到与所述基底（SUB）重叠的温度高于预定温度时，适于释放氢; c）固体形式的第三材料的第三结构（ST3），其适于在其经受电流时产生热能，从而至少被热耦合到所述第二结构（ST2）; 其中所述第一结构（ST1）和所述第二结构（ST2）至少部分地彼此接触。

5. 发明申请

WO1997020319A1 SOLID FUEL FOR COLD NUCLEAR FUSION REACTORS 审中-公开
标题翻译：固体燃料用于冷核燃烧反应堆
公开(公告)号：WO1997020319A1
公开(公告)日：1997-06-05
申请号：PCT/IT1996000225
申请日：1996-11-26
申请人： SGS-THOMSON MICROELECTRONICS S.R.L. , MASTROMATTEO, Ubaldo
发明人： SGS-THOMSON MICROELECTRONICS S.R.L.
IPC分类号： G21B01/00
CPC分类号： G21B3/00 , Y02E30/18
摘要： This invention relates to a solid fuel for cold nuclear fusion reactors. A reactor suitable for such fuel comprises a quantity (MA) of an absorbing material capable of absorbing hydrogen, and of generating in consequence thermal energy, has the form of a cylindrical container and comprises a quantity (CO) of a fuel capable of releasing hydrogen put in touch with the inner walls of container (MA), and comprises a thermal element (ET) located in the inside and in touch with fuel (CO) to heat it. The fuel according to this invention is constituted by a solid composition including at least one of the chemical elements belonging to the groups III, IV, V of the periodic system, or at least a compound obtained by combining to one another at least two of such elements, and including an effective quantity of hydrogen.
摘要翻译：本发明涉及用于冷核聚变反应堆的固体燃料。适用于这种燃料的反应器包括能够吸收氢并且由此产生热能的吸收材料的量（MA），其具有圆柱形容器的形式，并且包含能够释放氢的燃料的量（CO）与容器（MA）的内壁接触，并且包括位于内部并与燃料（CO）接触以加热它的热元件（ET）。根据本发明的燃料由固体组合物构成，所述固体组合物包括属于周期性体系的III，IV，V族的至少一种化学元素，或至少是通过将至少两种这样的元素，并包括有效量的氢。

6. 发明申请

WO1998012544A1 CONTACT MACRORADIOGRAPHY CHARACTERIZATION OF DOPED OPTICAL FIBERS 审中-公开
标题翻译：联系光学光学特性
公开(公告)号：WO1998012544A1
公开(公告)日：1998-03-26
申请号：PCT/IT1997000229
申请日：1997-09-19
申请人： SGS-THOMSON MICROELECTRONICS S.R.L. , SAVOIA, Claudio , MILANI, Marziale , SOTTOCASA, Emilia
发明人： SGS-THOMSON MICROELECTRONICS S.R.L.
IPC分类号： G01N23/04
CPC分类号： B82Y15/00 , G01N23/04
摘要： The doping of the core of an optical fiber may be precisely characterized by cutting sample slices of the fiber by means of a focused ion beam (FIB) machine and by carrying out a contact radiography of the slices using a soft X-ray source. Maps of the distribution of the dopant ions in the glassy matrix of the optical fiber's core may be obtained by analyzing the contact radiographies at the electronic or atomic force microscope. A dopant concentration value per unit length of fiber may be determined by interpolating the results over a plurality of slices of different thicknesses.
摘要翻译：可以通过聚焦离子束（FIB）机器切割光纤的样品切片并使用软X射线源进行切片的接触放射照相，可精确地表征光纤的纤芯的掺杂。通过分析电子或原子力显微镜下的接触X射线照片可以获得光纤芯的玻璃质基质中掺杂剂离子分布的图。可以通过在多个不同厚度的切片上内插结果来确定每单位纤维长度的掺杂剂浓度值。

7. 发明申请

WO1997049088A1 MULTI-LEVEL MEMORY CIRCUIT WITH REGULATED WRITING VOLTAGE 审中-公开
标题翻译：带监管写入电压的多级存储器电路
公开(公告)号：WO1997049088A1
公开(公告)日：1997-12-24
申请号：PCT/IT1996000199
申请日：1996-10-30
申请人： SGS-THOMSON MICROELECTRONICS S.R.L. , ROLANDI, Paolo
发明人： SGS-THOMSON MICROELECTRONICS S.R.L.
IPC分类号： G11C11/56
CPC分类号： G11C11/5621 , G11C5/145 , G11C11/5628 , G11C16/30
摘要： A multi-level memory circuit for binary information, according to the invention, comprises a plurality (MTX) of memory cells, each adapted to store more than one item of binary information and comprised of at least one floating gate MOS transistor, the information stored therein corresponding to the level of the cell threshold voltage, and a write signal generating circuit (ALIM) for the cell plurality, adapted to be input a supply voltage (VCC). The generating circuit (ALIM) is adapted to generate internally at least one write voltage (VW) having a selectable or selected (SW1, ..., SW4) value from a number of discrete regulated values corresponding to the number of the discrete levels provided.
摘要翻译：根据本发明的用于二进制信息的多级存储器电路包括多个（MTX）的存储器单元，每个存储单元适于存储多于一个二进制信息项，并且包括至少一个浮置栅极MOS晶体管，所存储的信息其中对应于单元阈值电压的电平，以及适用于输入电源电压（VCC）的单元多个的写信号生成电路（ALIM）。发生电路（ALIM）适于产生内部至少一个写入电压（VW），所述至少一个写入电压（VW）具有与所提供的离散电平的数量相对应的多个离散调节值的可选择或选择的（SW1，...，SW4）值。

8. 发明申请

WO1997020318A1 METHOD AND APPARATUS FOR THE GENERATION OF THERMAL ENERGY 审中-公开
标题翻译：用于产生热能的方法和装置
公开(公告)号：WO1997020318A1
公开(公告)日：1997-06-05
申请号：PCT/IT1996000224
申请日：1996-11-26
申请人： SGS-THOMSON MICROELECTRONICS S.R.L. , MASTROMATTEO, Ubaldo
发明人： SGS-THOMSON MICROELECTRONICS S.R.L.
IPC分类号： G21B01/00
CPC分类号： G21B3/00 , G21B3/002 , Y02E30/18
摘要： The apparatus for the generation of thermal energy according to this invention comprises: a) a first quantity (MA) in solid form of a first material suitable to absorb hydrogen with ensuing generation of thermal energy, b) a second quantity (CO) in solid form of a second material suitable to release hydrogen at a temperature higher than a prefixed temperature, at least partly in contact with said first quantity (MA), and c) a third quantity (ET) in solid form of a third material, suitable for the generation of thermal energy when it is submitted to the passage of electric current, so located as to be thermally coupled with said second quantity (CO).
摘要翻译：根据本发明的用于产生热能的装置包括：a）固体形式的第一材料的第一量（MA），其适合于随后产生热能吸收氢，b）固体中的第二量（CO）适于在高于预定温度的温度下释放氢的第二材料的形式，至少部分地与所述第一量（MA）接触，以及c）固体形式的第三材料的第三量（ET），适合于当热能通过电流时产生热能，所述热能定位成与所述第二量（CO）热耦合。

9. 发明授权

US6150853A Integrated unit gain output stage 失效
标题翻译：集成单位增益输出级
公开(公告)号：US6150853A
公开(公告)日：2000-11-21
申请号：US394688
申请日：1995-02-27
申请人： Francesco Chrappan , Maurizio Nessi , Alberto Salina
发明人： Francesco Chrappan , Maurizio Nessi , Alberto Salina
IPC分类号： H03F3/20 , H02P25/034 , H03F1/32 , H03F3/30 , H03F3/347 , H03K3/00
CPC分类号： H03F3/3062 , H02P25/034 , H03F1/3217 , H03F3/3037 , H03F2203/30057 , H03F2203/30096 , H03F2203/30129
摘要： The operation of externally connected output power transistors of a class AB amplifier is controlled without employing any external sensing resistance of the output current by driving an externally connected power transistor through a level shifting buffer and employing a limiting network composed of an integrated transistor driven by the output of a signal amplifying stage and a resistance connected in series with its drain. The buffer stage shifts the level of the driving signal of the external power transistor by a value equal to the threshold voltage of the integrated transistor of the limiting network thus ensuring the turn-off of the external power transistor under quiescent conditions.
摘要翻译：通过驱动外部连接的功率晶体管通过电平移位缓冲器来控制AB类放大器的外部连接的输出功率晶体管的操作，而不采用输出电流的任何外部感测电阻，并采用由由信号放大级的输出和与其漏极串联的电阻。缓冲级将外部功率晶体管的驱动信号的电平移动到等于限制网络的集成晶体管的阈值电压的值，从而确保在静态条件下外部功率晶体管的截止。

10. 发明授权

US6147380A Floating gate non-volatile memory cell with low erasing voltage and having different potential barriers 有权
标题翻译：具有低擦除电压并具有不同势垒的浮栅非易失性存储单元
公开(公告)号：US6147380A
公开(公告)日：2000-11-14
申请号：US521867
申请日：2000-03-08
申请人： Paolo Cappelletti
发明人： Paolo Cappelletti
IPC分类号： H01L21/8247 , H01L21/28 , H01L27/115 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28185 , H01L21/28176 , H01L21/28194 , H01L21/28202 , H01L21/2822 , H01L29/42332 , H01L29/42336 , H01L29/49 , H01L29/495 , H01L29/513 , H01L29/518
摘要： A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.
摘要翻译：包括至少一个浮栅晶体管并且在半导体衬底上实现的类型的非易失性存储单元包括源极区和漏极区，该沟道区由覆盖有栅极氧化物的薄层。栅极氧化物从衬底隔离浮栅区域。浮栅区域耦合到控制栅极端子。存储单元的浮置栅极区域在半导体衬底和栅极氧化物层之间形成第一势垒，并且在浮置栅极区域和栅极氧化物之间形成第二个不同的势垒。

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