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    • 1. 发明申请
    • FIBRE CHANNEL TRANSPARENT SWITCH FOR MIXED SWITCH FABRICS
    • 用于混合开关织物的光纤通道透明开关
    • WO2006041693A1
    • 2006-04-20
    • PCT/US2005/034845
    • 2005-09-27
    • QLOGIC CORPORATION
    • MCGLAUGHLIN, Edward C.
    • H04L12/56
    • H04L49/357H04L49/101H04L49/253H04L49/30
    • A method and a Fibre Channel switch element are provided that allows communication between a host system and a target device attached to a proprietary switch fabric in a network. The Fibre Channel switch element includes a first port that communicates with the target device through the proprietary switch fabric by logging on behalf of the host system so that the proprietary switch behaves as if it was directly communicating with the host system; and a second port that communicates with the host system and collects host bus adapter ("HBA") identification information, wherein the HBA identification information is used to map the first port to the second port so that when the host system communicates with the target device the Fibre Channel switch element is transparent to the proprietary switch fabric.
    • 提供了一种方法和光纤通道交换机元件,其允许主机系统和连接到网络中的专用交换机结构的目标设备之间的通信。 光纤通道交换机元件包括第一端口,其通过专用交换结构与目标设备进行通信,代表主机系统进行登录,使得专用交换机的行为就好像直接与主机系统通信; 以及与所述主机系统通信并收集主机总线适配器(“HBA”)识别信息的第二端口,其中所述HBA识别信息用于将所述第一端口映射到所述第二端口,使得当所述主机系统与所述目标设备通信时 光纤通道交换机元件对于专用交换矩阵是透明的。
    • 4. 发明申请
    • SYSTEM AND METHOD FOR TRANSMITTING DATA IN STORAGE CONTROLLERS
    • 用于传输存储控制器中的数据的系统和方法
    • WO2006019770A2
    • 2006-02-23
    • PCT/US2005/024774
    • 2005-07-13
    • QLOGIC CORPORATION
    • NGUYEN, Huy, T.KRANTZ, Leon, A.DENNIN, William, W.
    • G06F3/06
    • G06F3/0613G06F3/0656G06F3/0659G06F3/0676
    • A method and system for transferring frames from a storage device to a host system via a controller is provided. The method includes transferring frames from a transport module to a link module; and sending an acknowledgment to the transport module, wherein the link module sends the acknowledgement to the transport module and it appears to the transport module as if the host system sent the acknowledgement. The frames in the controller are tracked by creating a status entry indicating that a new frame is being created; accumulating data flow information, while a connection to transfer the frame is being established by a link module; and updating frame status as frame build is completed, transferred, and acknowledged. The controller includes, a header array in a transport module of the controller, wherein the header array includes plural layers and one of the layers is selected to process a frame.
    • 提供了一种用于经由控制器将帧从存储设备传送到主机系统的方法和系统。 该方法包括将帧从传输模块传输到链路模块; 以及向所述传输模块发送确认,其中所述链路模块向所述传输模块发送所述确认,并且所述传输模块对于所述主机系统看起来就好像所述主机系统发送了所述确认一样。 通过创建指示正在创建新帧的状态条目来跟踪控制器中的帧; 累积数据流信息,同时链路模块建立传输帧的连接; 并在帧构建完成,传输和确认时更新帧状态。 控制器包括控制器的传输模块中的头标阵列,其中头标阵列包括多个层,并且选择其中一个层来处理帧。
    • 6. 发明申请
    • METHOD AND SYSTEM FOR OPTIMIZING DMA CHANNEL SELECTION
    • 优化DMA信道选择的方法和系统
    • WO2006029133A2
    • 2006-03-16
    • PCT/US2005/031661
    • 2005-09-07
    • QLOGIC CORPORATION
    • SONKSEN, Bradley, S.CHU, Kuangfu, D.GANDHI, Rajendra, R.
    • G06F13/28
    • G06F13/28
    • A host bus adapter coupled to a network and a host computing system is provided. The host bus adapter includes a direct memory access (“DMA”) mode detection module that receives a DMA channel identifier information from an arbitration module that receives requests from plural DMA channels, wherein the DMA mode detection module includes a DMA counter that counts a number of times a single DMA channel is exclusively serviced by the arbitration module and if the DMA counter value is equal to a threshold value, then the DNA mode detection module enables a single channel mode during which standard transaction rules are ignored for determining DMA request lengths for transferring data. The single channel mode is enabled for a certain duration. The host bus adapter includes a rule based segmentation logic that may be enabled and/or disabled by host bus adapter firmware and/or detection of a single channel mode condition.
    • 提供耦合到网络和主机计算系统的主机总线适配器。 主机总线适配器包括从接收来自多个DMA通道的请求的仲裁模块接收DMA通道标识符信息的直接存储器访问(“DMA”)模式检测模块,其中DMA模式检测模块包括DMA计数器, 单个DMA通道由仲裁模块专门服务的时间,并且如果DMA计数器值等于阈值,则DNA模式检测模块启用单通道模式,在该模式期间忽略标准事务规则以确定DMA请求长度 传输数据。 单通道模式在一段时间内启用。 主机总线适配器包括基于规则的分段逻辑,其可以由主机总线适配器固件启用和/或禁用和/或检测单个通道模式条件。
    • 7. 发明申请
    • CIRCUIT AND METHOD FOR FILTERING OSCILLATIONS AND SYNCHRONIZING SIGNALS
    • 用于滤波振荡和同步信号的电路和方法
    • WO2001052015A2
    • 2001-07-19
    • PCT/US2001001376
    • 2001-01-16
    • QLOGIC CORPORATION
    • QLOGIC CORPORATIONVASHI, KevinDENNIN, William, W.
    • G06F
    • H03L7/00G11B20/1403H03K5/125H03K5/135
    • A filtering and synchronization circuit synchronizes an asynchronous input signal to a clock signal and generates a synchronous output signal. The circuit synchronizes both the leading edge and the trailing edge of the input signal and also blocks or filters out oscillations in the input signal for a period following the edges. The circuit includes an input signal latch which receives the input signal and provides a latched signal which does not change state even if the input signal subsequently changes state until the latched signal is synchronized to the clock signal. The circuit further includes a synchronizer which synchronizes the latched signal with the clock signal. The synchronizer provides feedback signals to the input signal latch to permit the input signal latch to recognize a change in the state of the input signal only after the synchronizer has synchronized the previous state of the input signal. The feedback signals can be selectively delayed to extend the time during which the input signal latch does not recognize changes in the state of the input signal.
    • 滤波和同步电路将异步输入信号与时钟信号同步并产生同步输出信号。 电路同步输入信号的前沿和后沿,并且在边沿之后的一段时间内阻塞或滤除输入信号中的振荡。 该电路包括输入信号锁存器,其接收输入信号并提供锁存信号,即使输入信号随后改变状态直到锁存信号与时钟信号同步,该信号也不改变状态。 电路还包括同步器,其将锁存的信号与时钟信号同步。 同步器向输入信号锁存器提供反馈信号,以允许输入信号锁存器仅在同步器已经同步输入信号的先前状态之后识别输入信号状态的变化。 可以选择性地延迟反馈信号以延长输入信号锁存器不识别输入信号状态的变化的时间。
    • 9. 发明申请
    • DYNAMIC WWN MODULE FOR STORAGE CONTROLLERS
    • 用于存储控制器的动态WWN模块
    • WO2006019807A2
    • 2006-02-23
    • PCT/US2005/024834
    • 2005-07-13
    • QLOGIC CORPORATION
    • KRANTZ, Leon, A.NGUYEN, KhaNORTH, Michael, J.
    • G06F3/06
    • G06F3/0659G06F3/0605G06F3/0676H04L29/12839H04L61/6022H04L69/22
    • A method and system for transferring data between a host and a Serial Attached Small Computer Interface ("SAS") device using a storage controller is provided. The storage controller includes, a World Wide Name ("WWN") module that includes a table having plural entries, wherein each row includes a WWN address, an initiator tag value field, an input/output counter value that tracks plural commands for a connection. A WWN index value represents the address of a row having plural entries. The method includes, comparing frame elements of incoming frames, including a unique WWN address with the WWN module entries; and if there is a match, updating a counter value for a connection between the storage controller and a device sending frames. The counter value is increased when a command frame is received and decreased when a command is executed and a response is sent to the device.
    • 提供了一种使用存储控制器在主机和串行连接小型计算机接口(“SAS”)设备之间传输数据的方法和系统。 存储控制器包括包括具有多个条目的表格的全球通用名称(“WWN”)模块,其中每行包括WWN地址,启动器标签值字段,跟踪多个命令的输入/输出计数器值,用于 连接。 WWN索引值表示具有多个条目的行的地址。 该方法包括:将输入帧的帧元素(包括唯一的WWN地址)与WWN模块条目进行比较; 如果匹配,则更新存储控制器与发送帧的设备之间的连接的计数器值。 当命令帧被接收时,计数器值增加,当命令执行并且响应被发送到设备时,计数器值减少。