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1. 发明专利

DE69519356D1 未知
公开(公告)号：DE69519356D1
公开(公告)日：2000-12-14
申请号：DE69519356
申请日：1995-09-27
申请人： PERICOM SEMICONDUCTOR CORP
发明人： WONG ANTHONY Y , KWONG DAVID , YANG LEE , HSIAO CHARLES
IPC分类号： H03K19/00 , H01L27/02 , H01L27/118 , H03K19/003 , H03K19/0175 , H03K19/0948
摘要： The output buffer output is coupled to a bus having low and high logic states. The high logic state corresp. to voltage at the first power supply voltage when the output buffer is driving the bus, and to voltage at second power supply higher than the first power supply voltage when the output buffer is not driving the bus and the output buffer is in the high-impedance state. The p-channel driver transistor pulls output high to first power supply voltage. A bias circuit comprising well bias device coupled to power supply and to output, couples N-well to first power supply when the output buffer is driving the bus. The well bias device couples the output to the N-well when the output buffer is not driving the bus and the bus is at the second power supply voltage higher than the first power supply voltage. An isolation engaging device coupled to well bias device signals when N-well is to be isolated from the first power supply and coupled to the output, and can signal N-well to be isolated from the first power supply when bus is at the second power supply voltage.

2. 发明专利

DE69519356T2 未知
公开(公告)号：DE69519356T2
公开(公告)日：2001-03-08
申请号：DE69519356
申请日：1995-09-27
申请人： PERICOM SEMICONDUCTOR CORP
发明人： WONG ANTHONY Y , KWONG DAVID , YANG LEE , HSIAO CHARLES
IPC分类号： H03K19/00 , H01L27/02 , H01L27/118 , H03K19/003 , H03K19/0175 , H03K19/0948
摘要： The output buffer output is coupled to a bus having low and high logic states. The high logic state corresp. to voltage at the first power supply voltage when the output buffer is driving the bus, and to voltage at second power supply higher than the first power supply voltage when the output buffer is not driving the bus and the output buffer is in the high-impedance state. The p-channel driver transistor pulls output high to first power supply voltage. A bias circuit comprising well bias device coupled to power supply and to output, couples N-well to first power supply when the output buffer is driving the bus. The well bias device couples the output to the N-well when the output buffer is not driving the bus and the bus is at the second power supply voltage higher than the first power supply voltage. An isolation engaging device coupled to well bias device signals when N-well is to be isolated from the first power supply and coupled to the output, and can signal N-well to be isolated from the first power supply when bus is at the second power supply voltage.

3. 发明专利

JPH08228139A ALL CMOS HIGH-IMPEDANCE OUTPUT BUFFER FOR BUS DRIVEN BY MULTIPLE POWER SUPPLY VOLTAGE 失效
公开(公告)号：JPH08228139A
公开(公告)日：1996-09-03
申请号：JP25616595
申请日：1995-10-03
申请人： PERICOM SEMICONDUCTOR CORP
发明人： WONG ANTHONY Y , KWONG DAVID , YANG LEE , HSIAO CHARLES
IPC分类号： H03K19/00 , H01L27/02 , H01L27/118 , H03K19/003 , H03K19/0175 , H03K19/0948
摘要： PROBLEM TO BE SOLVED: To reduce a diced area, and to reduce product costs by biasing an N well including a P channel driver transistor to a second power supply voltage when a bus voltage is substantially equal to the second power supply voltage. SOLUTION: A bus 12 is provided as an input to a bus circuit, and connected with a drain 30' of a P channel driver transistor Tr 18'. When the voltage of the bus 12 is substantially equal to a second power supply voltage, an N well 32' including the Tr 18' is biased to the second power supply voltage. Also, an output from an inverter is an input, the inverse of EN*VIN to Tr 51 and 52 forming a transmission gate 50. In this case, when the transmission gate 50 is provided, a gate 36' of the Tr 18' is biased to 5 V due to insulation, and the gate 36' of the Tr 18' can be insulated. Also, the drain of a transistor 53 is connected with the gate 36', and 5V is applied when insulated.

4. 发明公开

EP0706267A3 An all-CMOS high-impedance output buffer for a bus driven by multiple power-supply voltages 失效
标题翻译：为总线，其由多个电源电压驱动的CMOS高阻抗输出缓冲
公开(公告)号：EP0706267A3
公开(公告)日：1996-09-25
申请号：EP95115235.4
申请日：1995-09-27
申请人： Pericom Semiconductor Corp.
发明人： Wong, Anthony Y. , Kwong, David , Yang, Lee , Hsiao, Charles
IPC分类号： H03K19/003
CPC分类号： H03K19/00315 , H01L27/0218 , H01L27/11898 , H03K2217/0018
摘要： An all-CMOS output buffer drives a bus that can operate at 3 volts and 5 volts. When in a high-impedance state, the output buffer draws little or no current. If the bus is driven to 5 volts by an external device, the high impedance output buffer is in danger of latch-up and distortion of the bus logic level since it only has a 3-volt power supply and does not use a charge pump or an extra 5-volt supply. A biasing circuit couples an N-well that contains p-channel transistors and a driver transistor to the bus driven to 5 volts. Thus the N-well is also driven to 5 volts, the voltage on the bus. The gate of the p-channel driver transistor in the high-impedance output buffer is also coupled to the N-well by another p-channel transistor, raising the gate potential to 5 volts. Thus the gate and body of the p-channel driver transistor is at 5 volts, eliminating reversing current and latch-up problems. A transmission gate isolates the gate of the p-channel driver transistor from the rest of the device's circuitry. The p-channel transistors of the transmission gate, bias circuitry, and driver transistor are located in the N-well, which is biased up to 5 volts only when necessary. Thus during normal operation, the N-well of the driver transistor is at 3 volts, eliminating a performance loss from the body effect. A logic gate increases the well bias and isolates the driver's gate only when necessary, when the bus is high and driven by a 5-volt device, and the output buffer is in high-impedance.

5. 发明授权

EP0706267B1 An all-CMOS high-impedance output buffer for a bus driven by multiple power-supply voltages 失效
标题翻译：为总线，其由多个电源电压驱动的CMOS高阻抗输出缓冲
公开(公告)号：EP0706267B1
公开(公告)日：2000-11-08
申请号：EP95115235.4
申请日：1995-09-27
申请人： Pericom Semiconductor Corp.
发明人： Wong, Anthony Y. , Kwong, David , Yang, Lee , Hsiao, Charles
IPC分类号： H03K19/003
CPC分类号： H03K19/00315 , H01L27/0218 , H01L27/11898 , H03K2217/0018

6. 发明公开

EP0706267A2 An all-CMOS high-impedance output buffer for a bus driven by multiple power-supply voltages 失效
标题翻译：用于由多个电源电压驱动的总线的全CMOS高阻输出缓冲器
公开(公告)号：EP0706267A2
公开(公告)日：1996-04-10
申请号：EP95115235.4
申请日：1995-09-27
申请人： Pericom Semiconductor Corp.
发明人： Wong, Anthony Y. , Kwong, David , Yang, Lee , Hsiao, Charles
IPC分类号： H03K19/003
CPC分类号： H03K19/00315 , H01L27/0218 , H01L27/11898 , H03K2217/0018
摘要： An all-CMOS output buffer drives a bus that can operate at 3 volts and 5 volts. When in a high-impedance state, the output buffer draws little or no current. If the bus is driven to 5 volts by an external device, the high impedance output buffer is in danger of latch-up and distortion of the bus logic level since it only has a 3-volt power supply and does not use a charge pump or an extra 5-volt supply. A biasing circuit couples an N-well that contains p-channel transistors and a driver transistor to the bus driven to 5 volts. Thus the N-well is also driven to 5 volts, the voltage on the bus. The gate of the p-channel driver transistor in the high-impedance output buffer is also coupled to the N-well by another p-channel transistor, raising the gate potential to 5 volts. Thus the gate and body of the p-channel driver transistor is at 5 volts, eliminating reversing current and latch-up problems. A transmission gate isolates the gate of the p-channel driver transistor from the rest of the device's circuitry. The p-channel transistors of the transmission gate, bias circuitry, and driver transistor are located in the N-well, which is biased up to 5 volts only when necessary. Thus during normal operation, the N-well of the driver transistor is at 3 volts, eliminating a performance loss from the body effect. A logic gate increases the well bias and isolates the driver's gate only when necessary, when the bus is high and driven by a 5-volt device, and the output buffer is in high-impedance.
摘要翻译：全CMOS输出缓冲器驱动可在3伏和5伏电压下工作的总线。处于高阻状态时，输出缓冲区吸收很少或不吸收电流。如果总线由外部设备驱动至5伏，则高阻抗输出缓冲器存在闩锁和总线逻辑电平失真的危险，因为它仅具有3伏电源并且不使用电荷泵或额外的5伏电源。偏置电路将包含p沟道晶体管和驱动器晶体管的N阱耦合到驱动到5伏的总线。因此，N井也被驱动到5伏，即公交车上的电压。高阻抗输出缓冲器中的p沟道驱动器晶体管的栅极也通过另一个p沟道晶体管耦合到N阱，将栅极电位升高到5伏。因此，p沟道驱动器晶体管的栅极和本体电压为5伏，消除了反向电流和闩锁问题。传输门将P沟道驱动晶体管的栅极与器件的其他电路隔离开来。传输门，偏置电路和驱动器晶体管的p沟道晶体管位于N阱中，仅在需要时偏置至5伏。因此，在正常操作期间，驱动器晶体管的N阱处于3伏特，消除了身体效应的性能损失。逻辑门增加了阱偏压，并且只在必要时隔离驱动器的门极，当总线为高电平并由5伏器件驱动时，输出缓冲器处于高阻状态。

7. 发明申请

US20120235704A1 Redriver with Output Receiver Detection that Mirrors Detected Termination on Output to Input 有权
标题翻译：具有输出接收器检测的转接器检测到镜像检测到输出到输入的终止
公开(公告)号：US20120235704A1
公开(公告)日：2012-09-20
申请号：US13487100
申请日：2012-06-01
申请人： Tony Yeung , Michael Y. Zhang
发明人： Tony Yeung , Michael Y. Zhang
IPC分类号： H03K17/16
CPC分类号： H04L25/0278 , H03K19/0005 , H04B3/36 , H04L25/0272 , H04L25/0286 , H04L25/029 , H04L25/0298 , H04L25/03878
摘要： A redriver chip is inserted between a transmitter chip and a receiver chip and re-drives differential signals from the transmitter chip to the receiver chip. The redriver chip has switched output termination that switches to a high value to detect far-end termination at the receiver chip, and to a low value for signaling. An output detector detects when the receiver chip has termination to ground and enables switched input termination to provide termination to ground on the lines back to the transmitter chip so that the far-end termination on the receiver chip is mirrored back to the transmitter chip, hiding the redriver chip. An input signal detector detects when the transmitter chip begins signaling and enables an equalizer, limiter, pre-driver, and output stage to re-drive the signals to the receiver chip. The input signal detector also causes the switched output termination to switch to the low value termination for signaling.
摘要翻译：转发器芯片插入在发射机芯片和接收器芯片之间，并将差分信号从发射机芯片重新驱动到接收器芯片。转接芯片已切换输出端接，切换到高电平值，以检测接收芯片的远端终端，并发送信号低值。输出检测器检测接收器芯片何时终止接地并使能切换输入端接，以将线路上的终端提供给发射机芯片，使得接收器芯片上的远端终端被镜像回发射机芯片，隐藏转盘芯片。输入信号检测器检测发射机芯片什么时候开始发信号，并启用均衡器，限幅器，预驱动器和输出级，以将信号重新驱动到接收器芯片。输入信号检测器还使切换输出端接切换到低值终端用于信令。

8. 发明授权

US07332977B2 Crystal clock generator operating at third overtone of crystal's fundamental frequency 有权
标题翻译：晶体时钟发生器在晶体的基频第三次谐波处工作
公开(公告)号：US07332977B2
公开(公告)日：2008-02-19
申请号：US11306262
申请日：2005-12-21
申请人： Boris Drakhlis , Wing Faat Liu , Craig M. Taylor , Tony Yeung
发明人： Boris Drakhlis , Wing Faat Liu , Craig M. Taylor , Tony Yeung
IPC分类号： H03B27/00
CPC分类号： H03B5/36 , H03B5/06 , H03B5/364 , H03B2200/0008 , H03B2200/007 , H03B2200/0098
摘要： A crystal oscillator operates at the third overtone of the crystal's fundamental frequency. A value of a shunt resistor between the two phase-shift leg nodes is chosen so that the absolute value of the product gm×(Xc1)×(Xc2) is greater than the effective reactance of the crystal, where gm is the gain of the amplifier attached to the phase-shift legs, and Xc1 and Xc2 are the effective capacitive reactances of phase-shift legs at nodes X1 and X2. The third overtone is doubled by a multiplier and the final output filtered to remove the third overtone and select a frequency six times the fundamental frequency. A pair of Colpitts or Pierce amplifier half circuits is attached to the phase-shift leg nodes. The leg nodes can be capacitively isolated from Pierce-amplifier circuit nodes to improve start-up. Frequency doubling can be performed by summing currents from the two oscillator half circuits.
摘要翻译：晶体振荡器在晶体的基频的第三个泛音下工作。选择两个相移支路节点之间的分流电阻的值，使得乘积gmx（Xc 1）x（Xc 2）的绝对值大于晶体的有效电抗，其中gm是附接到相移支脚的放大器，Xc 1和Xc 2是节点X 1和X 2处的相移支脚的有效容抗。乘法器将第三个泛音加倍，滤波后的最终输出消除第三个泛音，并选择六倍于基频的频率。一对Colpitts或Pierce放大器半电路连接到相移腿节点。腿节点可以与Pierce放大器电路节点电容性隔离，以提高启动能力。可以通过对来自两个振荡器半电路的电流求和来执行倍频。

9. 发明授权

US06867957B1 Stacked-NMOS-triggered SCR device for ESD-protection 有权
标题翻译：用于ESD保护的堆叠NMOS触发SCR器件
公开(公告)号：US06867957B1
公开(公告)日：2005-03-15
申请号：US10065364
申请日：2002-10-09
申请人： Paul C. F. Tong , Ming-Dou Ker , Ping Ping Xu
发明人： Paul C. F. Tong , Ming-Dou Ker , Ping Ping Xu
IPC分类号： H01L27/02 , H02H9/00
CPC分类号： H01L27/0262 , H01L27/0266
摘要： Transistors with very thin gate oxides are protected against oxide failure by cascading two or more transistors in series between an output pad and ground. The intermediate source/drain node between the two cascaded transistors is usually floating during an ESD test, delaying snapback turn-on of a parasitic lateral NPN transistor. This intermediate node is used to drive the gate of an upper trigger transistor. A lower trigger transistor has a gate node that is charged by the ESD pulse on the pad through a coupling capacitor. When the coupled ESD pulse turns on the trigger transistors, the trigger transistors turn on a silicon-controlled rectifier (SCR) that is integrated with the trigger transistors.
摘要翻译：具有非常薄的栅极氧化物的晶体管通过在输出焊盘和接地之间串联两个或更多个晶体管来保护免受氧化物故障。两个级联晶体管之间的中间源极/漏极节点通常在ESD测试期间浮置，延迟了寄生侧面NPN晶体管的快速恢复导通。该中间节点用于驱动上触发晶体管的栅极。下触发晶体管具有通过耦合电容器通过焊盘上的ESD脉冲对其进行充电的栅极节点。当耦合的ESD脉冲接通触发晶体管时，触发晶体管导通与触发晶体管集成的可控硅整流器（SCR）。

10. 发明授权

US06842059B1 Muxed-output double-date-rate-2 (DDR2) register with fast propagation delay 失效
标题翻译：复用输出双倍速率2（DDR2）寄存器，具有快速的传播延迟
公开(公告)号：US06842059B1
公开(公告)日：2005-01-11
申请号：US10709132
申请日：2004-04-15
申请人： Ke Wu
发明人： Ke Wu
IPC分类号： H03K3/012 , H03K3/037 , H03K3/12
CPC分类号： H03K3/0372 , H03K3/012
摘要： A register chip for double-data-rate (DDR) memory modules operates in 1:1 mode or 1:2 mode. A differential input clock is buffered to generate a slave clock that continuously clocks slave stages of flip-flops, and gated to generate a first clock pulsing only in 1:1 mode and a second clock pulsing only in 1:2 mode. The master stage has two input transmission gates, one activated by the first clock and another activated by the second clock. In 1:1 mode a first data bit is sampled by the first clock, but in 1:2 mode a second data bit is sampled by the second clock. The sampled bit is inverted and applied to the slave stage and to a feedback gate that has transistors gated by the first and second clocks. The clock-to-output delay is improved since an output mux is replaced by the muxing function built into the master stage.
摘要翻译：用于双数据速率（DDR）存储器模块的寄存器芯片以1：1模式或1：2模式运行。差分输入时钟被缓冲以产生从时钟，其连续地触发触发器的从动级，并且门控仅产生以1：1模式脉冲的第一时钟脉冲，而第二时钟脉冲仅在1：2模式下脉冲。主级有两个输入传输门，一个由第一个时钟激活，另一个由第二个时钟激活。在1：1模式下，第一个数据位由第一个时钟采样，但在1：2模式下，第二个数据位由第二个时钟采样。采样位被反相并施加到从动级和具有由第一和第二时钟门控的晶体管的反馈门。时钟到输出延迟得到改善，因为输出多路复用器被内置于主机级的复用功能所代替。

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